Searched refs:IS_FPGA_MAXIMUS_DC (Results 1 – 25 of 28) sorted by relevance
12
69 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_translate_init()
71 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_factory_init()
112 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_clock()154 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_dispclk()
123 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce112_enable_display_power_gating()
135 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rv1_vbios_smu_set_dispclk()
421 if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dp_set_dsc_on_rx()471 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()498 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
3162 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in core_link_enable_stream()3632 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment)); in dc_link_is_fec_supported()
131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rn_vbios_smu_set_dispclk()
869 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in rn_clk_mgr_construct()923 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { in rn_clk_mgr_construct()
141 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_hw_sequencer_construct()
438 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()469 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()
141 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_hw_sequencer_construct()
2125 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_reset_back_end_for_pipe()
162 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce120_enable_display_power_gating()
147 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn21_hw_sequencer_construct()
1484 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { in dcn21_pp_smu_create()1794 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dcn21_resource_construct()2067 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn21_resource_construct()
72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ macro76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
513 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()525 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
479 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn20_clk_mgr_construct()
519 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn3_clk_mgr_construct()
883 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_reset_back_end_for_pipe()1269 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()1300 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()3058 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_prepare_bandwidth()3091 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_optimize_bandwidth()
1666 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn10_resource_construct()
892 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn21_dmcu_construct()
329 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()
909 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { in dce112_program_pix_clk()