Searched refs:IMX6SLL_CLK_PLL5_VIDEO_DIV (Results 1 – 2 of 2) sorted by relevance
57 #define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 macro
197 …hws[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post… in imx6sll_clocks_init()
