Searched refs:IMX27_CLK_PER1_GATE (Results 1 – 3 of 3) sorted by relevance
114 <&clks IMX27_CLK_PER1_GATE>;123 <&clks IMX27_CLK_PER1_GATE>;132 <&clks IMX27_CLK_PER1_GATE>;142 <&clks IMX27_CLK_PER1_GATE>;175 <&clks IMX27_CLK_PER1_GATE>;185 <&clks IMX27_CLK_PER1_GATE>;195 <&clks IMX27_CLK_PER1_GATE>;205 <&clks IMX27_CLK_PER1_GATE>;391 <&clks IMX27_CLK_PER1_GATE>;400 <&clks IMX27_CLK_PER1_GATE>;[all …]
70 #define IMX27_CLK_PER1_GATE 61 macro
53 &clk[IMX27_CLK_PER1_GATE],150 clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); in _mx27_clocks_init()
