Home
last modified time | relevance | path

Searched refs:IH_RB_CNTL (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dtonga_ih.c64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in tonga_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in tonga_ih_irq_init()
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); in tonga_ih_irq_init()
208 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_get_wptr()
Dvega10_ih.c51 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in vega10_ih_enable_interrupts()
52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts()
107 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in vega10_ih_disable_interrupts()
108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in vega10_ih_disable_interrupts()
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
180 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
182 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in vega10_ih_rb_cntl()
[all …]
Dsi_ih.c38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
43 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts()
49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
54 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts()
86 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_irq_init()
119 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
121 WREG32(IH_RB_CNTL, tmp); in si_ih_get_wptr()
Dnavi10_ih.c95 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in navi10_ih_enable_interrupts()
96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in navi10_ih_enable_interrupts()
152 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in navi10_ih_disable_interrupts()
153 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in navi10_ih_disable_interrupts()
215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
225 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
227 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in navi10_ih_rb_cntl()
[all …]
Diceland_ih.c66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init()
206 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_get_wptr()
Dcz_ih.c66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init()
206 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_get_wptr()
Dsid.h654 #define IH_RB_CNTL 0xF80 macro
/Linux-v5.10/drivers/gpu/drm/radeon/
Dr600.c3596 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts()
3601 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3607 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts()
3612 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3724 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
4058 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
4060 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
Dsi.c5923 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts()
5928 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5934 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts()
5939 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
6025 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
6228 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr()
6230 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
Dcik.c6826 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts()
6831 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6844 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts()
6849 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6993 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
7510 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr()
7512 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
Dsid.h651 #define IH_RB_CNTL 0x3e00 macro
Dcikd.h801 #define IH_RB_CNTL 0x3e00 macro
Devergreend.h1220 #define IH_RB_CNTL 0x3e00 macro
Dr600d.h659 #define IH_RB_CNTL 0x3e00 macro
Devergreen.c4694 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
4696 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()