1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 cx231xx-reg.h - driver for Conexant Cx23100/101/102 4 USB video capture devices 5 6 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 7 8 */ 9 10 #ifndef _CX231XX_REG_H 11 #define _CX231XX_REG_H 12 13 /***************************************************************************** 14 * VBI codes * 15 *****************************************************************************/ 16 17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80 18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90 19 20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0 21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0 22 23 #define SAV_VBLANK_FIELD1 0xa0 24 #define EAV_VBLANK_FIELD1 0xb0 25 26 #define SAV_VBLANK_FIELD2 0xe0 27 #define EAV_VBLANK_FIELD2 0xf0 28 29 #define SAV_VBI_FIELD1 0x20 30 #define EAV_VBI_FIELD1 0x30 31 32 #define SAV_VBI_FIELD2 0x60 33 #define EAV_VBI_FIELD2 0x70 34 35 /*****************************************************************************/ 36 /* Audio ADC Registers */ 37 #define CH_PWR_CTRL1 0x0000000e 38 #define CH_PWR_CTRL2 0x0000000f 39 /*****************************************************************************/ 40 41 #define HOST_REG1 0x000 42 #define FLD_FORCE_CHIP_SEL 0x80 43 #define FLD_AUTO_INC_DIS 0x20 44 #define FLD_PREFETCH_EN 0x10 45 /* Reserved [2:3] */ 46 #define FLD_DIGITAL_PWR_DN 0x02 47 #define FLD_SLEEP 0x01 48 49 /*****************************************************************************/ 50 #define HOST_REG2 0x001 51 52 /*****************************************************************************/ 53 #define HOST_REG3 0x002 54 55 /*****************************************************************************/ 56 /* added for polaris */ 57 #define GPIO_PIN_CTL0 0x3 58 #define GPIO_PIN_CTL1 0x4 59 #define GPIO_PIN_CTL2 0x5 60 #define GPIO_PIN_CTL3 0x6 61 #define TS1_PIN_CTL0 0x7 62 #define TS1_PIN_CTL1 0x8 63 /*****************************************************************************/ 64 65 #define FLD_CLK_IN_EN 0x80 66 #define FLD_XTAL_CTRL 0x70 67 #define FLD_BB_CLK_MODE 0x0C 68 #define FLD_REF_DIV_PLL 0x02 69 #define FLD_REF_SEL_PLL1 0x01 70 71 /*****************************************************************************/ 72 #define CHIP_CTRL 0x100 73 /* Reserved [27] */ 74 /* Reserved [31:21] */ 75 #define FLD_CHIP_ACFG_DIS 0x00100000 76 /* Reserved [19] */ 77 #define FLD_DUAL_MODE_ADC2 0x00040000 78 #define FLD_SIF_EN 0x00020000 79 #define FLD_SOFT_RST 0x00010000 80 #define FLD_DEVICE_ID 0x0000ffff 81 82 /*****************************************************************************/ 83 #define AFE_CTRL 0x104 84 #define AFE_CTRL_C2HH_SRC_CTRL 0x104 85 #define FLD_DIF_OUT_SEL 0xc0000000 86 #define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000 87 #define FLD_UV_ORDER_MODE 0x02000000 88 #define FLD_FUNC_MODE 0x01800000 89 #define FLD_ROT1_PHASE_CTL 0x007f8000 90 #define FLD_AUD_IN_SEL 0x00004000 91 #define FLD_LUMA_IN_SEL 0x00002000 92 #define FLD_CHROMA_IN_SEL 0x00001000 93 /* reserve [11:10] */ 94 #define FLD_INV_SPEC_DIS 0x00000200 95 #define FLD_VGA_SEL_CH3 0x00000100 96 #define FLD_VGA_SEL_CH2 0x00000080 97 #define FLD_VGA_SEL_CH1 0x00000040 98 #define FLD_DCR_BYP_CH1 0x00000020 99 #define FLD_DCR_BYP_CH2 0x00000010 100 #define FLD_DCR_BYP_CH3 0x00000008 101 #define FLD_EN_12DB_CH3 0x00000004 102 #define FLD_EN_12DB_CH2 0x00000002 103 #define FLD_EN_12DB_CH1 0x00000001 104 105 /* redefine in Cx231xx */ 106 /*****************************************************************************/ 107 #define DC_CTRL1 0x108 108 /* reserve [31:30] */ 109 #define FLD_CLAMP_LVL_CH1 0x3fff8000 110 #define FLD_CLAMP_LVL_CH2 0x00007fff 111 /*****************************************************************************/ 112 113 /*****************************************************************************/ 114 #define DC_CTRL2 0x10c 115 /* reserve [31:28] */ 116 #define FLD_CLAMP_LVL_CH3 0x00fffe00 117 #define FLD_CLAMP_WIND_LENTH 0x000001e0 118 #define FLD_C2HH_SAT_MIN 0x0000001e 119 #define FLD_FLT_BYP_SEL 0x00000001 120 /*****************************************************************************/ 121 122 /*****************************************************************************/ 123 #define DC_CTRL3 0x110 124 /* reserve [31:16] */ 125 #define FLD_ERR_GAIN_CTL 0x00070000 126 #define FLD_LPF_MIN 0x0000ffff 127 /*****************************************************************************/ 128 129 /*****************************************************************************/ 130 #define DC_CTRL4 0x114 131 /* reserve [31:31] */ 132 #define FLD_INTG_CH1 0x7fffffff 133 /*****************************************************************************/ 134 135 /*****************************************************************************/ 136 #define DC_CTRL5 0x118 137 /* reserve [31:31] */ 138 #define FLD_INTG_CH2 0x7fffffff 139 /*****************************************************************************/ 140 141 /*****************************************************************************/ 142 #define DC_CTRL6 0x11c 143 /* reserve [31:31] */ 144 #define FLD_INTG_CH3 0x7fffffff 145 /*****************************************************************************/ 146 147 /*****************************************************************************/ 148 #define PIN_CTRL 0x120 149 #define FLD_OEF_AGC_RF 0x00000001 150 #define FLD_OEF_AGC_IFVGA 0x00000002 151 #define FLD_OEF_AGC_IF 0x00000004 152 #define FLD_REG_BO_PUD 0x80000000 153 #define FLD_IR_IRQ_STAT 0x40000000 154 #define FLD_AUD_IRQ_STAT 0x20000000 155 #define FLD_VID_IRQ_STAT 0x10000000 156 /* Reserved [27:26] */ 157 #define FLD_IRQ_N_OUT_EN 0x02000000 158 #define FLD_IRQ_N_POLAR 0x01000000 159 /* Reserved [23:6] */ 160 #define FLD_OE_AUX_PLL_CLK 0x00000020 161 #define FLD_OE_I2S_BCLK 0x00000010 162 #define FLD_OE_I2S_WCLK 0x00000008 163 #define FLD_OE_AGC_IF 0x00000004 164 #define FLD_OE_AGC_IFVGA 0x00000002 165 #define FLD_OE_AGC_RF 0x00000001 166 167 /*****************************************************************************/ 168 #define AUD_IO_CTRL 0x124 169 /* Reserved [31:8] */ 170 #define FLD_I2S_PORT_DIR 0x00000080 171 #define FLD_I2S_OUT_SRC 0x00000040 172 #define FLD_AUD_CHAN3_SRC 0x00000030 173 #define FLD_AUD_CHAN2_SRC 0x0000000c 174 #define FLD_AUD_CHAN1_SRC 0x00000003 175 176 /*****************************************************************************/ 177 #define AUD_LOCK1 0x128 178 #define FLD_AUD_LOCK_KI_SHIFT 0xc0000000 179 #define FLD_AUD_LOCK_KD_SHIFT 0x30000000 180 /* Reserved [27:25] */ 181 #define FLD_EN_AV_LOCK 0x01000000 182 #define FLD_VID_COUNT 0x00ffffff 183 184 /*****************************************************************************/ 185 #define AUD_LOCK2 0x12c 186 #define FLD_AUD_LOCK_KI_MULT 0xf0000000 187 #define FLD_AUD_LOCK_KD_MULT 0x0F000000 188 /* Reserved [23:22] */ 189 #define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 190 #define FLD_AUD_COUNT 0x000fffff 191 192 /*****************************************************************************/ 193 #define AFE_DIAG_CTRL1 0x134 194 /* Reserved [31:16] */ 195 #define FLD_CUV_DLY_LENGTH 0x0000ff00 196 #define FLD_YC_DLY_LENGTH 0x000000ff 197 198 /*****************************************************************************/ 199 /* Poalris redefine */ 200 #define AFE_DIAG_CTRL3 0x138 201 /* Reserved [31:26] */ 202 #define FLD_AUD_DUAL_FLAG_POL 0x02000000 203 #define FLD_VID_DUAL_FLAG_POL 0x01000000 204 /* Reserved [23:23] */ 205 #define FLD_COL_CLAMP_DIS_CH1 0x00400000 206 #define FLD_COL_CLAMP_DIS_CH2 0x00200000 207 #define FLD_COL_CLAMP_DIS_CH3 0x00100000 208 209 #define TEST_CTRL1 0x144 210 /* Reserved [31:29] */ 211 #define FLD_LBIST_EN 0x10000000 212 /* Reserved [27:10] */ 213 #define FLD_FI_BIST_INTR_R 0x0000200 214 #define FLD_FI_BIST_INTR_L 0x0000100 215 #define FLD_BIST_FAIL_AUD_PLL 0x0000080 216 #define FLD_BIST_INTR_AUD_PLL 0x0000040 217 #define FLD_BIST_FAIL_VID_PLL 0x0000020 218 #define FLD_BIST_INTR_VID_PLL 0x0000010 219 /* Reserved [3:1] */ 220 #define FLD_CIR_TEST_DIS 0x00000001 221 222 /*****************************************************************************/ 223 #define TEST_CTRL2 0x148 224 #define FLD_TSXCLK_POL_CTL 0x80000000 225 #define FLD_ISO_CTL_SEL 0x40000000 226 #define FLD_ISO_CTL_EN 0x20000000 227 #define FLD_BIST_DEBUGZ 0x10000000 228 #define FLD_AUD_BIST_TEST_H 0x0f000000 229 /* Reserved [23:22] */ 230 #define FLD_FLTRN_BIST_TEST_H 0x00020000 231 #define FLD_VID_BIST_TEST_H 0x00010000 232 /* Reserved [19:17] */ 233 #define FLD_BIST_TEST_H 0x00010000 234 /* Reserved [15:13] */ 235 #define FLD_TAB_EN 0x00001000 236 /* Reserved [11:0] */ 237 238 /*****************************************************************************/ 239 #define BIST_STAT 0x14c 240 #define FLD_AUD_BIST_FAIL_H 0xfff00000 241 #define FLD_FLTRN_BIST_FAIL_H 0x00180000 242 #define FLD_VID_BIST_FAIL_H 0x00070000 243 #define FLD_AUD_BIST_TST_DONE 0x0000fff0 244 #define FLD_FLTRN_BIST_TST_DONE 0x00000008 245 #define FLD_VID_BIST_TST_DONE 0x00000007 246 247 /*****************************************************************************/ 248 /* DirectIF registers definition have been moved to DIF_reg.h */ 249 /*****************************************************************************/ 250 #define MODE_CTRL 0x400 251 #define FLD_AFD_PAL60_DIS 0x20000000 252 #define FLD_AFD_FORCE_SECAM 0x10000000 253 #define FLD_AFD_FORCE_PALNC 0x08000000 254 #define FLD_AFD_FORCE_PAL 0x04000000 255 #define FLD_AFD_PALM_SEL 0x03000000 256 #define FLD_CKILL_MODE 0x00300000 257 #define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ 258 #define FLD_CLR_LOCK_STAT 0x00020000 259 #define FLD_FAST_LOCK_MD 0x00010000 260 #define FLD_WCEN 0x00008000 261 #define FLD_CAGCEN 0x00004000 262 #define FLD_CKILLEN 0x00002000 263 #define FLD_AUTO_SC_LOCK 0x00001000 264 #define FLD_MAN_SC_FAST_LOCK 0x00000800 265 #define FLD_INPUT_MODE 0x00000600 266 #define FLD_AFD_ACQUIRE 0x00000100 267 #define FLD_AFD_NTSC_SEL 0x00000080 268 #define FLD_AFD_PAL_SEL 0x00000040 269 #define FLD_ACFG_DIS 0x00000020 270 #define FLD_SQ_PIXEL 0x00000010 271 #define FLD_VID_FMT_SEL 0x0000000f 272 273 /*****************************************************************************/ 274 #define OUT_CTRL1 0x404 275 #define FLD_POLAR 0x7f000000 276 /* Reserved [23] */ 277 #define FLD_RND_MODE 0x00600000 278 #define FLD_VIPCLAMP_EN 0x00100000 279 #define FLD_VIPBLANK_EN 0x00080000 280 #define FLD_VIP_OPT_AL 0x00040000 281 #define FLD_IDID0_SOURCE 0x00020000 282 #define FLD_DCMODE 0x00010000 283 #define FLD_CLK_GATING 0x0000c000 284 #define FLD_CLK_INVERT 0x00002000 285 #define FLD_HSFMT 0x00001000 286 #define FLD_VALIDFMT 0x00000800 287 #define FLD_ACTFMT 0x00000400 288 #define FLD_SWAPRAW 0x00000200 289 #define FLD_CLAMPRAW_EN 0x00000100 290 #define FLD_BLUE_FIELD_EN 0x00000080 291 #define FLD_BLUE_FIELD_ACT 0x00000040 292 #define FLD_TASKBIT_VAL 0x00000020 293 #define FLD_ANC_DATA_EN 0x00000010 294 #define FLD_VBIHACTRAW_EN 0x00000008 295 #define FLD_MODE10B 0x00000004 296 #define FLD_OUT_MODE 0x00000003 297 298 /*****************************************************************************/ 299 #define OUT_CTRL2 0x408 300 #define FLD_AUD_GRP 0xc0000000 301 #define FLD_SAMPLE_RATE 0x30000000 302 #define FLD_AUD_ANC_EN 0x08000000 303 #define FLD_EN_C 0x04000000 304 #define FLD_EN_B 0x02000000 305 #define FLD_EN_A 0x01000000 306 /* Reserved [23:20] */ 307 #define FLD_IDID1_LSB 0x000c0000 308 #define FLD_IDID0_LSB 0x00030000 309 #define FLD_IDID1_MSB 0x0000ff00 310 #define FLD_IDID0_MSB 0x000000ff 311 312 /*****************************************************************************/ 313 #define GEN_STAT 0x40c 314 #define FLD_VCR_DETECT 0x00800000 315 #define FLD_SPECIAL_PLAY_N 0x00400000 316 #define FLD_VPRES 0x00200000 317 #define FLD_AGC_LOCK 0x00100000 318 #define FLD_CSC_LOCK 0x00080000 319 #define FLD_VLOCK 0x00040000 320 #define FLD_SRC_LOCK 0x00020000 321 #define FLD_HLOCK 0x00010000 322 #define FLD_VSYNC_N 0x00008000 323 #define FLD_SRC_FIFO_UFLOW 0x00004000 324 #define FLD_SRC_FIFO_OFLOW 0x00002000 325 #define FLD_FIELD 0x00001000 326 #define FLD_AFD_FMT_STAT 0x00000f00 327 #define FLD_MV_TYPE2_PAIR 0x00000080 328 #define FLD_MV_T3CS 0x00000040 329 #define FLD_MV_CS 0x00000020 330 #define FLD_MV_PSP 0x00000010 331 /* Reserved [3] */ 332 #define FLD_MV_CDAT 0x00000003 333 334 /*****************************************************************************/ 335 #define INT_STAT_MASK 0x410 336 #define FLD_COMB_3D_FIFO_MSK 0x80000000 337 #define FLD_WSS_DAT_AVAIL_MSK 0x40000000 338 #define FLD_GS2_DAT_AVAIL_MSK 0x20000000 339 #define FLD_GS1_DAT_AVAIL_MSK 0x10000000 340 #define FLD_CC_DAT_AVAIL_MSK 0x08000000 341 #define FLD_VPRES_CHANGE_MSK 0x04000000 342 #define FLD_MV_CHANGE_MSK 0x02000000 343 #define FLD_END_VBI_EVEN_MSK 0x01000000 344 #define FLD_END_VBI_ODD_MSK 0x00800000 345 #define FLD_FMT_CHANGE_MSK 0x00400000 346 #define FLD_VSYNC_TRAIL_MSK 0x00200000 347 #define FLD_HLOCK_CHANGE_MSK 0x00100000 348 #define FLD_VLOCK_CHANGE_MSK 0x00080000 349 #define FLD_CSC_LOCK_CHANGE_MSK 0x00040000 350 #define FLD_SRC_FIFO_UFLOW_MSK 0x00020000 351 #define FLD_SRC_FIFO_OFLOW_MSK 0x00010000 352 #define FLD_COMB_3D_FIFO_STAT 0x00008000 353 #define FLD_WSS_DAT_AVAIL_STAT 0x00004000 354 #define FLD_GS2_DAT_AVAIL_STAT 0x00002000 355 #define FLD_GS1_DAT_AVAIL_STAT 0x00001000 356 #define FLD_CC_DAT_AVAIL_STAT 0x00000800 357 #define FLD_VPRES_CHANGE_STAT 0x00000400 358 #define FLD_MV_CHANGE_STAT 0x00000200 359 #define FLD_END_VBI_EVEN_STAT 0x00000100 360 #define FLD_END_VBI_ODD_STAT 0x00000080 361 #define FLD_FMT_CHANGE_STAT 0x00000040 362 #define FLD_VSYNC_TRAIL_STAT 0x00000020 363 #define FLD_HLOCK_CHANGE_STAT 0x00000010 364 #define FLD_VLOCK_CHANGE_STAT 0x00000008 365 #define FLD_CSC_LOCK_CHANGE_STAT 0x00000004 366 #define FLD_SRC_FIFO_UFLOW_STAT 0x00000002 367 #define FLD_SRC_FIFO_OFLOW_STAT 0x00000001 368 369 /*****************************************************************************/ 370 #define LUMA_CTRL 0x414 371 #define BRIGHTNESS_CTRL_BYTE 0x414 372 #define CONTRAST_CTRL_BYTE 0x415 373 #define LUMA_CTRL_BYTE_3 0x416 374 #define FLD_LUMA_CORE_SEL 0x00c00000 375 #define FLD_RANGE 0x00300000 376 /* Reserved [19] */ 377 #define FLD_PEAK_EN 0x00040000 378 #define FLD_PEAK_SEL 0x00030000 379 #define FLD_CNTRST 0x0000ff00 380 #define FLD_BRITE 0x000000ff 381 382 /*****************************************************************************/ 383 #define HSCALE_CTRL 0x418 384 #define FLD_HFILT 0x03000000 385 #define FLD_HSCALE 0x00ffffff 386 387 /*****************************************************************************/ 388 #define VSCALE_CTRL 0x41c 389 #define FLD_LINE_AVG_DIS 0x01000000 390 /* Reserved [23:20] */ 391 #define FLD_VS_INTRLACE 0x00080000 392 #define FLD_VFILT 0x00070000 393 /* Reserved [15:13] */ 394 #define FLD_VSCALE 0x00001fff 395 396 /*****************************************************************************/ 397 #define CHROMA_CTRL 0x420 398 #define USAT_CTRL_BYTE 0x420 399 #define VSAT_CTRL_BYTE 0x421 400 #define HUE_CTRL_BYTE 0x422 401 #define FLD_C_LPF_EN 0x20000000 402 #define FLD_CHR_DELAY 0x1c000000 403 #define FLD_C_CORE_SEL 0x03000000 404 #define FLD_HUE 0x00ff0000 405 #define FLD_VSAT 0x0000ff00 406 #define FLD_USAT 0x000000ff 407 408 /*****************************************************************************/ 409 #define VBI_LINE_CTRL1 0x424 410 #define FLD_VBI_MD_LINE4 0xff000000 411 #define FLD_VBI_MD_LINE3 0x00ff0000 412 #define FLD_VBI_MD_LINE2 0x0000ff00 413 #define FLD_VBI_MD_LINE1 0x000000ff 414 415 /*****************************************************************************/ 416 #define VBI_LINE_CTRL2 0x428 417 #define FLD_VBI_MD_LINE8 0xff000000 418 #define FLD_VBI_MD_LINE7 0x00ff0000 419 #define FLD_VBI_MD_LINE6 0x0000ff00 420 #define FLD_VBI_MD_LINE5 0x000000ff 421 422 /*****************************************************************************/ 423 #define VBI_LINE_CTRL3 0x42c 424 #define FLD_VBI_MD_LINE12 0xff000000 425 #define FLD_VBI_MD_LINE11 0x00ff0000 426 #define FLD_VBI_MD_LINE10 0x0000ff00 427 #define FLD_VBI_MD_LINE9 0x000000ff 428 429 /*****************************************************************************/ 430 #define VBI_LINE_CTRL4 0x430 431 #define FLD_VBI_MD_LINE16 0xff000000 432 #define FLD_VBI_MD_LINE15 0x00ff0000 433 #define FLD_VBI_MD_LINE14 0x0000ff00 434 #define FLD_VBI_MD_LINE13 0x000000ff 435 436 /*****************************************************************************/ 437 #define VBI_LINE_CTRL5 0x434 438 #define FLD_VBI_MD_LINE17 0x000000ff 439 440 /*****************************************************************************/ 441 #define VBI_FC_CFG 0x438 442 #define FLD_FC_ALT2 0xff000000 443 #define FLD_FC_ALT1 0x00ff0000 444 #define FLD_FC_ALT2_TYPE 0x0000f000 445 #define FLD_FC_ALT1_TYPE 0x00000f00 446 /* Reserved [7:1] */ 447 #define FLD_FC_SEARCH_MODE 0x00000001 448 449 /*****************************************************************************/ 450 #define VBI_MISC_CFG1 0x43c 451 #define FLD_TTX_PKTADRU 0xfff00000 452 #define FLD_TTX_PKTADRL 0x000fff00 453 /* Reserved [7:6] */ 454 #define FLD_MOJI_PACK_DIS 0x00000020 455 #define FLD_VPS_DEC_DIS 0x00000010 456 #define FLD_CRI_MARG_SCALE 0x0000000c 457 #define FLD_EDGE_RESYNC_EN 0x00000002 458 #define FLD_ADAPT_SLICE_DIS 0x00000001 459 460 /*****************************************************************************/ 461 #define VBI_MISC_CFG2 0x440 462 #define FLD_HAMMING_TYPE 0x0f000000 463 /* Reserved [23:20] */ 464 #define FLD_WSS_FIFO_RST 0x00080000 465 #define FLD_GS2_FIFO_RST 0x00040000 466 #define FLD_GS1_FIFO_RST 0x00020000 467 #define FLD_CC_FIFO_RST 0x00010000 468 /* Reserved [15:12] */ 469 #define FLD_VBI3_SDID 0x00000f00 470 #define FLD_VBI2_SDID 0x000000f0 471 #define FLD_VBI1_SDID 0x0000000f 472 473 /*****************************************************************************/ 474 #define VBI_PAY1 0x444 475 #define FLD_GS1_FIFO_DAT 0xFF000000 476 #define FLD_GS1_STAT 0x00FF0000 477 #define FLD_CC_FIFO_DAT 0x0000FF00 478 #define FLD_CC_STAT 0x000000FF 479 480 /*****************************************************************************/ 481 #define VBI_PAY2 0x448 482 #define FLD_WSS_FIFO_DAT 0xff000000 483 #define FLD_WSS_STAT 0x00ff0000 484 #define FLD_GS2_FIFO_DAT 0x0000ff00 485 #define FLD_GS2_STAT 0x000000ff 486 487 /*****************************************************************************/ 488 #define VBI_CUST1_CFG1 0x44c 489 /* Reserved [31] */ 490 #define FLD_VBI1_CRIWIN 0x7f000000 491 #define FLD_VBI1_SLICE_DIST 0x00f00000 492 #define FLD_VBI1_BITINC 0x000fff00 493 #define FLD_VBI1_HDELAY 0x000000ff 494 495 /*****************************************************************************/ 496 #define VBI_CUST1_CFG2 0x450 497 #define FLD_VBI1_FC_LENGTH 0x1f000000 498 #define FLD_VBI1_FRAME_CODE 0x00ffffff 499 500 /*****************************************************************************/ 501 #define VBI_CUST1_CFG3 0x454 502 #define FLD_VBI1_HAM_EN 0x80000000 503 #define FLD_VBI1_FIFO_MODE 0x70000000 504 #define FLD_VBI1_FORMAT_TYPE 0x0f000000 505 #define FLD_VBI1_PAYLD_LENGTH 0x00ff0000 506 #define FLD_VBI1_CRI_LENGTH 0x0000f000 507 #define FLD_VBI1_CRI_MARGIN 0x00000f00 508 #define FLD_VBI1_CRI_TIME 0x000000ff 509 510 /*****************************************************************************/ 511 #define VBI_CUST2_CFG1 0x458 512 /* Reserved [31] */ 513 #define FLD_VBI2_CRIWIN 0x7f000000 514 #define FLD_VBI2_SLICE_DIST 0x00f00000 515 #define FLD_VBI2_BITINC 0x000fff00 516 #define FLD_VBI2_HDELAY 0x000000ff 517 518 /*****************************************************************************/ 519 #define VBI_CUST2_CFG2 0x45c 520 #define FLD_VBI2_FC_LENGTH 0x1f000000 521 #define FLD_VBI2_FRAME_CODE 0x00ffffff 522 523 /*****************************************************************************/ 524 #define VBI_CUST2_CFG3 0x460 525 #define FLD_VBI2_HAM_EN 0x80000000 526 #define FLD_VBI2_FIFO_MODE 0x70000000 527 #define FLD_VBI2_FORMAT_TYPE 0x0f000000 528 #define FLD_VBI2_PAYLD_LENGTH 0x00ff0000 529 #define FLD_VBI2_CRI_LENGTH 0x0000f000 530 #define FLD_VBI2_CRI_MARGIN 0x00000f00 531 #define FLD_VBI2_CRI_TIME 0x000000ff 532 533 /*****************************************************************************/ 534 #define VBI_CUST3_CFG1 0x464 535 /* Reserved [31] */ 536 #define FLD_VBI3_CRIWIN 0x7f000000 537 #define FLD_VBI3_SLICE_DIST 0x00f00000 538 #define FLD_VBI3_BITINC 0x000fff00 539 #define FLD_VBI3_HDELAY 0x000000ff 540 541 /*****************************************************************************/ 542 #define VBI_CUST3_CFG2 0x468 543 #define FLD_VBI3_FC_LENGTH 0x1f000000 544 #define FLD_VBI3_FRAME_CODE 0x00ffffff 545 546 /*****************************************************************************/ 547 #define VBI_CUST3_CFG3 0x46c 548 #define FLD_VBI3_HAM_EN 0x80000000 549 #define FLD_VBI3_FIFO_MODE 0x70000000 550 #define FLD_VBI3_FORMAT_TYPE 0x0f000000 551 #define FLD_VBI3_PAYLD_LENGTH 0x00ff0000 552 #define FLD_VBI3_CRI_LENGTH 0x0000f000 553 #define FLD_VBI3_CRI_MARGIN 0x00000f00 554 #define FLD_VBI3_CRI_TIME 0x000000ff 555 556 /*****************************************************************************/ 557 #define HORIZ_TIM_CTRL 0x470 558 #define FLD_BGDEL_CNT 0xff000000 559 /* Reserved [23:22] */ 560 #define FLD_HACTIVE_CNT 0x003ff000 561 /* Reserved [11:10] */ 562 #define FLD_HBLANK_CNT 0x000003ff 563 564 /*****************************************************************************/ 565 #define VERT_TIM_CTRL 0x474 566 #define FLD_V656BLANK_CNT 0xff000000 567 /* Reserved [23:22] */ 568 #define FLD_VACTIVE_CNT 0x003ff000 569 /* Reserved [11:10] */ 570 #define FLD_VBLANK_CNT 0x000003ff 571 572 /*****************************************************************************/ 573 #define SRC_COMB_CFG 0x478 574 #define FLD_CCOMB_2LN_CHECK 0x80000000 575 #define FLD_CCOMB_3LN_EN 0x40000000 576 #define FLD_CCOMB_2LN_EN 0x20000000 577 #define FLD_CCOMB_3D_EN 0x10000000 578 /* Reserved [27] */ 579 #define FLD_LCOMB_3LN_EN 0x04000000 580 #define FLD_LCOMB_2LN_EN 0x02000000 581 #define FLD_LCOMB_3D_EN 0x01000000 582 #define FLD_LUMA_LPF_SEL 0x00c00000 583 #define FLD_UV_LPF_SEL 0x00300000 584 #define FLD_BLEND_SLOPE 0x000f0000 585 #define FLD_CCOMB_REDUCE_EN 0x00008000 586 /* Reserved [14:10] */ 587 #define FLD_SRC_DECIM_RATIO 0x000003ff 588 589 /*****************************************************************************/ 590 #define CHROMA_VBIOFF_CFG 0x47c 591 #define FLD_VBI_VOFFSET 0x1f000000 592 /* Reserved [23:20] */ 593 #define FLD_SC_STEP 0x000fffff 594 595 /*****************************************************************************/ 596 #define FIELD_COUNT 0x480 597 #define FLD_FIELD_COUNT_FLD 0x000003ff 598 599 /*****************************************************************************/ 600 #define MISC_TIM_CTRL 0x484 601 #define FLD_DEBOUNCE_COUNT 0xc0000000 602 #define FLD_VT_LINE_CNT_HYST 0x30000000 603 /* Reserved [27] */ 604 #define FLD_AFD_STAT 0x07ff0000 605 #define FLD_VPRES_VERT_EN 0x00008000 606 /* Reserved [14:12] */ 607 #define FLD_HR32 0x00000800 608 #define FLD_TDALGN 0x00000400 609 #define FLD_TDFIELD 0x00000200 610 /* Reserved [8:6] */ 611 #define FLD_TEMPDEC 0x0000003f 612 613 /*****************************************************************************/ 614 #define DFE_CTRL1 0x488 615 #define FLD_CLAMP_AUTO_EN 0x80000000 616 #define FLD_AGC_AUTO_EN 0x40000000 617 #define FLD_VGA_CRUSH_EN 0x20000000 618 #define FLD_VGA_AUTO_EN 0x10000000 619 #define FLD_VBI_GATE_EN 0x08000000 620 #define FLD_CLAMP_LEVEL 0x07000000 621 /* Reserved [23:22] */ 622 #define FLD_CLAMP_SKIP_CNT 0x00300000 623 #define FLD_AGC_GAIN 0x000fff00 624 /* Reserved [7:6] */ 625 #define FLD_VGA_GAIN 0x0000003f 626 627 /*****************************************************************************/ 628 #define DFE_CTRL2 0x48c 629 #define FLD_VGA_ACQUIRE_RANGE 0x00ff0000 630 #define FLD_VGA_TRACK_RANGE 0x0000ff00 631 #define FLD_VGA_SYNC 0x000000ff 632 633 /*****************************************************************************/ 634 #define DFE_CTRL3 0x490 635 #define FLD_BP_PERCENT 0xff000000 636 #define FLD_DFT_THRESHOLD 0x00ff0000 637 /* Reserved [15:12] */ 638 #define FLD_SYNC_WIDTH_SEL 0x00000600 639 #define FLD_BP_LOOP_GAIN 0x00000300 640 #define FLD_SYNC_LOOP_GAIN 0x000000c0 641 /* Reserved [5:4] */ 642 #define FLD_AGC_LOOP_GAIN 0x0000000c 643 #define FLD_DCC_LOOP_GAIN 0x00000003 644 645 /*****************************************************************************/ 646 #define PLL_CTRL 0x494 647 #define FLD_PLL_KD 0xff000000 648 #define FLD_PLL_KI 0x00ff0000 649 #define FLD_PLL_MAX_OFFSET 0x0000ffff 650 651 /*****************************************************************************/ 652 #define HTL_CTRL 0x498 653 /* Reserved [31:24] */ 654 #define FLD_AUTO_LOCK_SPD 0x00080000 655 #define FLD_MAN_FAST_LOCK 0x00040000 656 #define FLD_HTL_15K_EN 0x00020000 657 #define FLD_HTL_500K_EN 0x00010000 658 #define FLD_HTL_KD 0x0000ff00 659 #define FLD_HTL_KI 0x000000ff 660 661 /*****************************************************************************/ 662 #define COMB_CTRL 0x49c 663 #define FLD_COMB_PHASE_LIMIT 0xff000000 664 #define FLD_CCOMB_ERR_LIMIT 0x00ff0000 665 #define FLD_LUMA_THRESHOLD 0x0000ff00 666 #define FLD_LCOMB_ERR_LIMIT 0x000000ff 667 668 /*****************************************************************************/ 669 #define CRUSH_CTRL 0x4a0 670 #define FLD_WTW_EN 0x00400000 671 #define FLD_CRUSH_FREQ 0x00200000 672 #define FLD_MAJ_SEL_EN 0x00100000 673 #define FLD_MAJ_SEL 0x000c0000 674 /* Reserved [17:15] */ 675 #define FLD_SYNC_TIP_REDUCE 0x00007e00 676 /* Reserved [8:6] */ 677 #define FLD_SYNC_TIP_INC 0x0000003f 678 679 /*****************************************************************************/ 680 #define SOFT_RST_CTRL 0x4a4 681 #define FLD_VD_SOFT_RST 0x00008000 682 /* Reserved [14:12] */ 683 #define FLD_REG_RST_MSK 0x00000800 684 #define FLD_VOF_RST_MSK 0x00000400 685 #define FLD_MVDET_RST_MSK 0x00000200 686 #define FLD_VBI_RST_MSK 0x00000100 687 #define FLD_SCALE_RST_MSK 0x00000080 688 #define FLD_CHROMA_RST_MSK 0x00000040 689 #define FLD_LUMA_RST_MSK 0x00000020 690 #define FLD_VTG_RST_MSK 0x00000010 691 #define FLD_YCSEP_RST_MSK 0x00000008 692 #define FLD_SRC_RST_MSK 0x00000004 693 #define FLD_DFE_RST_MSK 0x00000002 694 /* Reserved [0] */ 695 696 /*****************************************************************************/ 697 #define MV_DT_CTRL1 0x4a8 698 /* Reserved [31:29] */ 699 #define FLD_PSP_STOP_LINE 0x1f000000 700 /* Reserved [23:21] */ 701 #define FLD_PSP_STRT_LINE 0x001f0000 702 /* Reserved [15] */ 703 #define FLD_PSP_LLIMW 0x00007f00 704 /* Reserved [7] */ 705 #define FLD_PSP_ULIMW 0x0000007f 706 707 /*****************************************************************************/ 708 #define MV_DT_CTRL2 0x4aC 709 #define FLD_CS_STOPWIN 0xff000000 710 #define FLD_CS_STRTWIN 0x00ff0000 711 #define FLD_CS_WIDTH 0x0000ff00 712 #define FLD_PSP_SPEC_VAL 0x000000ff 713 714 /*****************************************************************************/ 715 #define MV_DT_CTRL3 0x4B0 716 #define FLD_AUTO_RATE_DIS 0x80000000 717 #define FLD_HLOCK_DIS 0x40000000 718 #define FLD_SEL_FIELD_CNT 0x20000000 719 #define FLD_CS_TYPE2_SEL 0x10000000 720 #define FLD_CS_LINE_THRSH_SEL 0x08000000 721 #define FLD_CS_ATHRESH_SEL 0x04000000 722 #define FLD_PSP_SPEC_SEL 0x02000000 723 #define FLD_PSP_LINES_SEL 0x01000000 724 #define FLD_FIELD_CNT 0x00f00000 725 #define FLD_CS_TYPE2_CNT 0x000fc000 726 #define FLD_CS_LINE_CNT 0x00003f00 727 #define FLD_CS_ATHRESH_LEV 0x000000ff 728 729 /*****************************************************************************/ 730 #define CHIP_VERSION 0x4b4 731 /* Cx231xx redefine */ 732 #define VERSION 0x4b4 733 #define FLD_REV_ID 0x000000ff 734 735 /*****************************************************************************/ 736 #define MISC_DIAG_CTRL 0x4b8 737 /* Reserved [31:24] */ 738 #define FLD_SC_CONVERGE_THRESH 0x00ff0000 739 #define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00 740 #define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff 741 742 /*****************************************************************************/ 743 #define VBI_PASS_CTRL 0x4bc 744 #define FLD_VBI_PASS_MD 0x00200000 745 #define FLD_VBI_SETUP_DIS 0x00100000 746 #define FLD_PASS_LINE_CTRL 0x000fffff 747 748 /*****************************************************************************/ 749 /* Cx231xx redefine */ 750 #define VCR_DET_CTRL 0x4c0 751 #define FLD_EN_FIELD_PHASE_DET 0x80000000 752 #define FLD_EN_HEAD_SW_DET 0x40000000 753 #define FLD_FIELD_PHASE_LENGTH 0x01ff0000 754 /* Reserved [29:25] */ 755 #define FLD_FIELD_PHASE_DELAY 0x0000ff00 756 #define FLD_FIELD_PHASE_LIMIT 0x000000f0 757 #define FLD_HEAD_SW_DET_LIMIT 0x0000000f 758 759 /*****************************************************************************/ 760 #define DL_CTL 0x800 761 #define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ 762 #define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ 763 #define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ 764 #define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ 765 /* Reserved [31:5] */ 766 #define FLD_START_8051 0x10000000 767 #define FLD_DL_ENABLE 0x08000000 768 #define FLD_DL_AUTO_INC 0x04000000 769 #define FLD_DL_MAP 0x03000000 770 771 /*****************************************************************************/ 772 #define STD_DET_STATUS 0x804 773 #define FLD_SPARE_STATUS1 0xff000000 774 #define FLD_SPARE_STATUS0 0x00ff0000 775 #define FLD_MOD_DET_STATUS1 0x0000ff00 776 #define FLD_MOD_DET_STATUS0 0x000000ff 777 778 /*****************************************************************************/ 779 #define AUD_BUILD_NUM 0x806 780 #define AUD_VER_NUM 0x807 781 #define STD_DET_CTL 0x808 782 #define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ 783 #define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ 784 #define FLD_SPARE_CTL0 0xff000000 785 #define FLD_DIS_DBX 0x00800000 786 #define FLD_DIS_BTSC 0x00400000 787 #define FLD_DIS_NICAM_A2 0x00200000 788 #define FLD_VIDEO_PRESENT 0x00100000 789 #define FLD_DW8051_VIDEO_FORMAT 0x000f0000 790 #define FLD_PREF_DEC_MODE 0x0000ff00 791 #define FLD_AUD_CONFIG 0x000000ff 792 793 /*****************************************************************************/ 794 #define DW8051_INT 0x80c 795 #define FLD_VIDEO_PRESENT_CHANGE 0x80000000 796 #define FLD_VIDEO_CHANGE 0x40000000 797 #define FLD_RDS_READY 0x20000000 798 #define FLD_AC97_INT 0x10000000 799 #define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000 800 #define FLD_NICAM_LOCK 0x04000000 801 #define FLD_NICAM_UNLOCK 0x02000000 802 #define FLD_DFT4_TH_CMP 0x01000000 803 /* Reserved [23:22] */ 804 #define FLD_LOCK_IND_INT 0x00200000 805 #define FLD_DFT3_TH_CMP 0x00100000 806 #define FLD_DFT2_TH_CMP 0x00080000 807 #define FLD_DFT1_TH_CMP 0x00040000 808 #define FLD_FM2_DFT_TH_CMP 0x00020000 809 #define FLD_FM1_DFT_TH_CMP 0x00010000 810 #define FLD_VIDEO_PRESENT_EN 0x00008000 811 #define FLD_VIDEO_CHANGE_EN 0x00004000 812 #define FLD_RDS_READY_EN 0x00002000 813 #define FLD_AC97_INT_EN 0x00001000 814 #define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800 815 #define FLD_NICAM_LOCK_EN 0x00000400 816 #define FLD_NICAM_UNLOCK_EN 0x00000200 817 #define FLD_DFT4_TH_CMP_EN 0x00000100 818 /* Reserved [7] */ 819 #define FLD_DW8051_INT6_CTL1 0x00000040 820 #define FLD_DW8051_INT5_CTL1 0x00000020 821 #define FLD_DW8051_INT4_CTL1 0x00000010 822 #define FLD_DW8051_INT3_CTL1 0x00000008 823 #define FLD_DW8051_INT2_CTL1 0x00000004 824 #define FLD_DW8051_INT1_CTL1 0x00000002 825 #define FLD_DW8051_INT0_CTL1 0x00000001 826 827 /*****************************************************************************/ 828 #define GENERAL_CTL 0x810 829 #define FLD_RDS_INT 0x80000000 830 #define FLD_NBER_INT 0x40000000 831 #define FLD_NLL_INT 0x20000000 832 #define FLD_IFL_INT 0x10000000 833 #define FLD_FDL_INT 0x08000000 834 #define FLD_AFC_INT 0x04000000 835 #define FLD_AMC_INT 0x02000000 836 #define FLD_AC97_INT_CTL 0x01000000 837 #define FLD_RDS_INT_DIS 0x00800000 838 #define FLD_NBER_INT_DIS 0x00400000 839 #define FLD_NLL_INT_DIS 0x00200000 840 #define FLD_IFL_INT_DIS 0x00100000 841 #define FLD_FDL_INT_DIS 0x00080000 842 #define FLD_FC_INT_DIS 0x00040000 843 #define FLD_AMC_INT_DIS 0x00020000 844 #define FLD_AC97_INT_DIS 0x00010000 845 #define FLD_REV_NUM 0x0000ff00 846 /* Reserved [7:5] */ 847 #define FLD_DBX_SOFT_RESET_REG 0x00000010 848 #define FLD_AD_SOFT_RESET_REG 0x00000008 849 #define FLD_SRC_SOFT_RESET_REG 0x00000004 850 #define FLD_CDMOD_SOFT_RESET 0x00000002 851 #define FLD_8051_SOFT_RESET 0x00000001 852 853 /*****************************************************************************/ 854 #define AAGC_CTL 0x814 855 #define FLD_AFE_12DB_EN 0x80000000 856 #define FLD_AAGC_DEFAULT_EN 0x40000000 857 #define FLD_AAGC_DEFAULT 0x3f000000 858 /* Reserved [23] */ 859 #define FLD_AAGC_GAIN 0x00600000 860 #define FLD_AAGC_TH 0x001f0000 861 /* Reserved [15:14] */ 862 #define FLD_AAGC_HYST2 0x00003f00 863 /* Reserved [7:6] */ 864 #define FLD_AAGC_HYST1 0x0000003f 865 866 /*****************************************************************************/ 867 #define IF_SRC_CTL 0x818 868 #define FLD_DBX_BYPASS 0x80000000 869 /* Reserved [30:25] */ 870 #define FLD_IF_SRC_MODE 0x01000000 871 /* Reserved [23:18] */ 872 #define FLD_IF_SRC_PHASE_INC 0x0001ffff 873 874 /*****************************************************************************/ 875 #define ANALOG_DEMOD_CTL 0x81c 876 #define FLD_ROT1_PHACC_PROG 0xffff0000 877 /* Reserved [15] */ 878 #define FLD_FM1_DELAY_FIX 0x00007000 879 #define FLD_PDF4_SHIFT 0x00000c00 880 #define FLD_PDF3_SHIFT 0x00000300 881 #define FLD_PDF2_SHIFT 0x000000c0 882 #define FLD_PDF1_SHIFT 0x00000030 883 #define FLD_FMBYPASS_MODE2 0x00000008 884 #define FLD_FMBYPASS_MODE1 0x00000004 885 #define FLD_NICAM_MODE 0x00000002 886 #define FLD_BTSC_FMRADIO_MODE 0x00000001 887 888 /*****************************************************************************/ 889 #define ROT_FREQ_CTL 0x820 890 #define FLD_ROT3_PHACC_PROG 0xffff0000 891 #define FLD_ROT2_PHACC_PROG 0x0000ffff 892 893 /*****************************************************************************/ 894 #define FM_CTL 0x824 895 #define FLD_FM2_DC_FB_SHIFT 0xf0000000 896 #define FLD_FM2_DC_INT_SHIFT 0x0f000000 897 #define FLD_FM2_AFC_RESET 0x00800000 898 #define FLD_FM2_DC_PASS_IN 0x00400000 899 #define FLD_FM2_DAGC_SHIFT 0x00380000 900 #define FLD_FM2_CORDIC_SHIFT 0x00070000 901 #define FLD_FM1_DC_FB_SHIFT 0x0000f000 902 #define FLD_FM1_DC_INT_SHIFT 0x00000f00 903 #define FLD_FM1_AFC_RESET 0x00000080 904 #define FLD_FM1_DC_PASS_IN 0x00000040 905 #define FLD_FM1_DAGC_SHIFT 0x00000038 906 #define FLD_FM1_CORDIC_SHIFT 0x00000007 907 908 /*****************************************************************************/ 909 #define LPF_PDF_CTL 0x828 910 /* Reserved [31:30] */ 911 #define FLD_LPF32_SHIFT1 0x30000000 912 #define FLD_LPF32_SHIFT2 0x0c000000 913 #define FLD_LPF160_SHIFTA 0x03000000 914 #define FLD_LPF160_SHIFTB 0x00c00000 915 #define FLD_LPF160_SHIFTC 0x00300000 916 #define FLD_LPF32_COEF_SEL2 0x000c0000 917 #define FLD_LPF32_COEF_SEL1 0x00030000 918 #define FLD_LPF160_COEF_SELC 0x0000c000 919 #define FLD_LPF160_COEF_SELB 0x00003000 920 #define FLD_LPF160_COEF_SELA 0x00000c00 921 #define FLD_LPF160_IN_EN_REG 0x00000300 922 #define FLD_PDF4_PDF_SEL 0x000000c0 923 #define FLD_PDF3_PDF_SEL 0x00000030 924 #define FLD_PDF2_PDF_SEL 0x0000000c 925 #define FLD_PDF1_PDF_SEL 0x00000003 926 927 /*****************************************************************************/ 928 #define DFT1_CTL1 0x82c 929 #define FLD_DFT1_DWELL 0xffff0000 930 #define FLD_DFT1_FREQ 0x0000ffff 931 932 /*****************************************************************************/ 933 #define DFT1_CTL2 0x830 934 #define FLD_DFT1_THRESHOLD 0xffffff00 935 #define FLD_DFT1_CMP_CTL 0x00000080 936 #define FLD_DFT1_AVG 0x00000070 937 /* Reserved [3:1] */ 938 #define FLD_DFT1_START 0x00000001 939 940 /*****************************************************************************/ 941 #define DFT1_STATUS 0x834 942 #define FLD_DFT1_DONE 0x80000000 943 #define FLD_DFT1_TH_CMP_STAT 0x40000000 944 #define FLD_DFT1_RESULT 0x3fffffff 945 946 /*****************************************************************************/ 947 #define DFT2_CTL1 0x838 948 #define FLD_DFT2_DWELL 0xffff0000 949 #define FLD_DFT2_FREQ 0x0000ffff 950 951 /*****************************************************************************/ 952 #define DFT2_CTL2 0x83C 953 #define FLD_DFT2_THRESHOLD 0xffffff00 954 #define FLD_DFT2_CMP_CTL 0x00000080 955 #define FLD_DFT2_AVG 0x00000070 956 /* Reserved [3:1] */ 957 #define FLD_DFT2_START 0x00000001 958 959 /*****************************************************************************/ 960 #define DFT2_STATUS 0x840 961 #define FLD_DFT2_DONE 0x80000000 962 #define FLD_DFT2_TH_CMP_STAT 0x40000000 963 #define FLD_DFT2_RESULT 0x3fffffff 964 965 /*****************************************************************************/ 966 #define DFT3_CTL1 0x844 967 #define FLD_DFT3_DWELL 0xffff0000 968 #define FLD_DFT3_FREQ 0x0000ffff 969 970 /*****************************************************************************/ 971 #define DFT3_CTL2 0x848 972 #define FLD_DFT3_THRESHOLD 0xffffff00 973 #define FLD_DFT3_CMP_CTL 0x00000080 974 #define FLD_DFT3_AVG 0x00000070 975 /* Reserved [3:1] */ 976 #define FLD_DFT3_START 0x00000001 977 978 /*****************************************************************************/ 979 #define DFT3_STATUS 0x84c 980 #define FLD_DFT3_DONE 0x80000000 981 #define FLD_DFT3_TH_CMP_STAT 0x40000000 982 #define FLD_DFT3_RESULT 0x3fffffff 983 984 /*****************************************************************************/ 985 #define DFT4_CTL1 0x850 986 #define FLD_DFT4_DWELL 0xffff0000 987 #define FLD_DFT4_FREQ 0x0000ffff 988 989 /*****************************************************************************/ 990 #define DFT4_CTL2 0x854 991 #define FLD_DFT4_THRESHOLD 0xffffff00 992 #define FLD_DFT4_CMP_CTL 0x00000080 993 #define FLD_DFT4_AVG 0x00000070 994 /* Reserved [3:1] */ 995 #define FLD_DFT4_START 0x00000001 996 997 /*****************************************************************************/ 998 #define DFT4_STATUS 0x858 999 #define FLD_DFT4_DONE 0x80000000 1000 #define FLD_DFT4_TH_CMP_STAT 0x40000000 1001 #define FLD_DFT4_RESULT 0x3fffffff 1002 1003 /*****************************************************************************/ 1004 #define AM_MTS_DET 0x85c 1005 #define FLD_AM_MTS_MODE 0x80000000 1006 /* Reserved [30:26] */ 1007 #define FLD_AM_SUB 0x02000000 1008 #define FLD_AM_GAIN_EN 0x01000000 1009 /* Reserved [23:16] */ 1010 #define FLD_AMMTS_GAIN_SCALE 0x0000e000 1011 #define FLD_MTS_PDF_SHIFT 0x00001800 1012 #define FLD_AM_REG_GAIN 0x00000700 1013 #define FLD_AGC_REF 0x000000ff 1014 1015 /*****************************************************************************/ 1016 #define ANALOG_MUX_CTL 0x860 1017 /* Reserved [31:29] */ 1018 #define FLD_MUX21_SEL 0x10000000 1019 #define FLD_MUX20_SEL 0x08000000 1020 #define FLD_MUX19_SEL 0x04000000 1021 #define FLD_MUX18_SEL 0x02000000 1022 #define FLD_MUX17_SEL 0x01000000 1023 #define FLD_MUX16_SEL 0x00800000 1024 #define FLD_MUX15_SEL 0x00400000 1025 #define FLD_MUX14_SEL 0x00300000 1026 #define FLD_MUX13_SEL 0x000C0000 1027 #define FLD_MUX12_SEL 0x00020000 1028 #define FLD_MUX11_SEL 0x00018000 1029 #define FLD_MUX10_SEL 0x00004000 1030 #define FLD_MUX9_SEL 0x00002000 1031 #define FLD_MUX8_SEL 0x00001000 1032 #define FLD_MUX7_SEL 0x00000800 1033 #define FLD_MUX6_SEL 0x00000600 1034 #define FLD_MUX5_SEL 0x00000100 1035 #define FLD_MUX4_SEL 0x000000c0 1036 #define FLD_MUX3_SEL 0x00000030 1037 #define FLD_MUX2_SEL 0x0000000c 1038 #define FLD_MUX1_SEL 0x00000003 1039 1040 /*****************************************************************************/ 1041 /* Cx231xx redefine */ 1042 #define DPLL_CTRL1 0x864 1043 #define DIG_PLL_CTL1 0x864 1044 1045 #define FLD_PLL_STATUS 0x07000000 1046 #define FLD_BANDWIDTH_SELECT 0x00030000 1047 #define FLD_PLL_SHIFT_REG 0x00007000 1048 #define FLD_PHASE_SHIFT 0x000007ff 1049 1050 /*****************************************************************************/ 1051 /* Cx231xx redefine */ 1052 #define DPLL_CTRL2 0x868 1053 #define DIG_PLL_CTL2 0x868 1054 #define FLD_PLL_UNLOCK_THR 0xff000000 1055 #define FLD_PLL_LOCK_THR 0x00ff0000 1056 /* Reserved [15:8] */ 1057 #define FLD_AM_PDF_SEL2 0x000000c0 1058 #define FLD_AM_PDF_SEL1 0x00000030 1059 #define FLD_DPLL_FSM_CTRL 0x0000000c 1060 /* Reserved [1] */ 1061 #define FLD_PLL_PILOT_DET 0x00000001 1062 1063 /*****************************************************************************/ 1064 /* Cx231xx redefine */ 1065 #define DPLL_CTRL3 0x86c 1066 #define DIG_PLL_CTL3 0x86c 1067 #define FLD_DISABLE_LOOP 0x01000000 1068 #define FLD_A1_DS1_SEL 0x000c0000 1069 #define FLD_A1_DS2_SEL 0x00030000 1070 #define FLD_A1_KI 0x0000ff00 1071 #define FLD_A1_KD 0x000000ff 1072 1073 /*****************************************************************************/ 1074 /* Cx231xx redefine */ 1075 #define DPLL_CTRL4 0x870 1076 #define DIG_PLL_CTL4 0x870 1077 #define FLD_A2_DS1_SEL 0x000c0000 1078 #define FLD_A2_DS2_SEL 0x00030000 1079 #define FLD_A2_KI 0x0000ff00 1080 #define FLD_A2_KD 0x000000ff 1081 1082 /*****************************************************************************/ 1083 /* Cx231xx redefine */ 1084 #define DPLL_CTRL5 0x874 1085 #define DIG_PLL_CTL5 0x874 1086 #define FLD_TRK_DS1_SEL 0x000c0000 1087 #define FLD_TRK_DS2_SEL 0x00030000 1088 #define FLD_TRK_KI 0x0000ff00 1089 #define FLD_TRK_KD 0x000000ff 1090 1091 /*****************************************************************************/ 1092 #define DEEMPH_GAIN_CTL 0x878 1093 #define FLD_DEEMPH2_GAIN 0xFFFF0000 1094 #define FLD_DEEMPH1_GAIN 0x0000FFFF 1095 1096 /*****************************************************************************/ 1097 /* Cx231xx redefine */ 1098 #define DEEMPH_COEFF1 0x87c 1099 #define DEEMPH_COEF1 0x87c 1100 #define FLD_DEEMPH_B0 0xffff0000 1101 #define FLD_DEEMPH_A0 0x0000ffff 1102 1103 /*****************************************************************************/ 1104 /* Cx231xx redefine */ 1105 #define DEEMPH_COEFF2 0x880 1106 #define DEEMPH_COEF2 0x880 1107 #define FLD_DEEMPH_B1 0xFFFF0000 1108 #define FLD_DEEMPH_A1 0x0000FFFF 1109 1110 /*****************************************************************************/ 1111 #define DBX1_CTL1 0x884 1112 #define FLD_DBX1_WBE_GAIN 0xffff0000 1113 #define FLD_DBX1_IN_GAIN 0x0000ffff 1114 1115 /*****************************************************************************/ 1116 #define DBX1_CTL2 0x888 1117 #define FLD_DBX1_SE_BYPASS 0xffff0000 1118 #define FLD_DBX1_SE_GAIN 0x0000ffff 1119 1120 /*****************************************************************************/ 1121 #define DBX1_RMS_SE 0x88C 1122 #define FLD_DBX1_RMS_WBE 0xffff0000 1123 #define FLD_DBX1_RMS_SE_FLD 0x0000ffff 1124 1125 /*****************************************************************************/ 1126 #define DBX2_CTL1 0x890 1127 #define FLD_DBX2_WBE_GAIN 0xffff0000 1128 #define FLD_DBX2_IN_GAIN 0x0000ffff 1129 1130 /*****************************************************************************/ 1131 #define DBX2_CTL2 0x894 1132 #define FLD_DBX2_SE_BYPASS 0xffff0000 1133 #define FLD_DBX2_SE_GAIN 0x0000ffff 1134 1135 /*****************************************************************************/ 1136 #define DBX2_RMS_SE 0x898 1137 #define FLD_DBX2_RMS_WBE 0xffff0000 1138 #define FLD_DBX2_RMS_SE_FLD 0x0000ffff 1139 1140 /*****************************************************************************/ 1141 #define AM_FM_DIFF 0x89c 1142 /* Reserved [31] */ 1143 #define FLD_FM_DIFF_OUT 0x7fff0000 1144 /* Reserved [15] */ 1145 #define FLD_AM_DIFF_OUT 0x00007fff 1146 1147 /*****************************************************************************/ 1148 #define NICAM_FAW 0x8a0 1149 #define FLD_FAWDETWINEND 0xFc000000 1150 #define FLD_FAWDETWINSTR 0x03ff0000 1151 /* Reserved [15:12] */ 1152 #define FLD_FAWDETTHRSHLD3 0x00000f00 1153 #define FLD_FAWDETTHRSHLD2 0x000000f0 1154 #define FLD_FAWDETTHRSHLD1 0x0000000f 1155 1156 /*****************************************************************************/ 1157 /* Cx231xx redefine */ 1158 #define DEEMPH_GAIN 0x8a4 1159 #define NICAM_DEEMPHGAIN 0x8a4 1160 /* Reserved [31:18] */ 1161 #define FLD_DEEMPHGAIN 0x0003ffff 1162 1163 /*****************************************************************************/ 1164 /* Cx231xx redefine */ 1165 #define DEEMPH_NUMER1 0x8a8 1166 #define NICAM_DEEMPHNUMER1 0x8a8 1167 /* Reserved [31:18] */ 1168 #define FLD_DEEMPHNUMER1 0x0003ffff 1169 1170 /*****************************************************************************/ 1171 /* Cx231xx redefine */ 1172 #define DEEMPH_NUMER2 0x8ac 1173 #define NICAM_DEEMPHNUMER2 0x8ac 1174 /* Reserved [31:18] */ 1175 #define FLD_DEEMPHNUMER2 0x0003ffff 1176 1177 /*****************************************************************************/ 1178 /* Cx231xx redefine */ 1179 #define DEEMPH_DENOM1 0x8b0 1180 #define NICAM_DEEMPHDENOM1 0x8b0 1181 /* Reserved [31:18] */ 1182 #define FLD_DEEMPHDENOM1 0x0003ffff 1183 1184 /*****************************************************************************/ 1185 /* Cx231xx redefine */ 1186 #define DEEMPH_DENOM2 0x8b4 1187 #define NICAM_DEEMPHDENOM2 0x8b4 1188 /* Reserved [31:18] */ 1189 #define FLD_DEEMPHDENOM2 0x0003ffff 1190 1191 /*****************************************************************************/ 1192 #define NICAM_ERRLOG_CTL1 0x8B8 1193 /* Reserved [31:28] */ 1194 #define FLD_ERRINTRPTTHSHLD1 0x0fff0000 1195 /* Reserved [15:12] */ 1196 #define FLD_ERRLOGPERIOD 0x00000fff 1197 1198 /*****************************************************************************/ 1199 #define NICAM_ERRLOG_CTL2 0x8bc 1200 /* Reserved [31:28] */ 1201 #define FLD_ERRINTRPTTHSHLD3 0x0fff0000 1202 /* Reserved [15:12] */ 1203 #define FLD_ERRINTRPTTHSHLD2 0x00000fff 1204 1205 /*****************************************************************************/ 1206 #define NICAM_ERRLOG_STS1 0x8c0 1207 /* Reserved [31:28] */ 1208 #define FLD_ERRLOG2 0x0fff0000 1209 /* Reserved [15:12] */ 1210 #define FLD_ERRLOG1 0x00000fff 1211 1212 /*****************************************************************************/ 1213 #define NICAM_ERRLOG_STS2 0x8c4 1214 /* Reserved [31:12] */ 1215 #define FLD_ERRLOG3 0x00000fff 1216 1217 /*****************************************************************************/ 1218 #define NICAM_STATUS 0x8c8 1219 /* Reserved [31:20] */ 1220 #define FLD_NICAM_CIB 0x000c0000 1221 #define FLD_NICAM_LOCK_STAT 0x00020000 1222 #define FLD_NICAM_MUTE 0x00010000 1223 #define FLD_NICAMADDIT_DATA 0x0000ffe0 1224 #define FLD_NICAMCNTRL 0x0000001f 1225 1226 /*****************************************************************************/ 1227 #define DEMATRIX_CTL 0x8cc 1228 #define FLD_AC97_IN_SHIFT 0xf0000000 1229 #define FLD_I2S_IN_SHIFT 0x0f000000 1230 #define FLD_DEMATRIX_SEL_CTL 0x00ff0000 1231 /* Reserved [15:11] */ 1232 #define FLD_DMTRX_BYPASS 0x00000400 1233 #define FLD_DEMATRIX_MODE 0x00000300 1234 /* Reserved [7:6] */ 1235 #define FLD_PH_DBX_SEL 0x00000020 1236 #define FLD_PH_CH_SEL 0x00000010 1237 #define FLD_PHASE_FIX 0x0000000f 1238 1239 /*****************************************************************************/ 1240 #define PATH1_CTL1 0x8d0 1241 /* Reserved [31:29] */ 1242 #define FLD_PATH1_MUTE_CTL 0x1f000000 1243 /* Reserved [23:22] */ 1244 #define FLD_PATH1_AVC_CG 0x00300000 1245 #define FLD_PATH1_AVC_RT 0x000f0000 1246 #define FLD_PATH1_AVC_AT 0x0000f000 1247 #define FLD_PATH1_AVC_STEREO 0x00000800 1248 #define FLD_PATH1_AVC_CR 0x00000700 1249 #define FLD_PATH1_AVC_RMS_CON 0x000000f0 1250 #define FLD_PATH1_SEL_CTL 0x0000000f 1251 1252 /*****************************************************************************/ 1253 #define PATH1_VOL_CTL 0x8d4 1254 #define FLD_PATH1_AVC_THRESHOLD 0x7fff0000 1255 #define FLD_PATH1_BAL_LEFT 0x00008000 1256 #define FLD_PATH1_BAL_LEVEL 0x00007f00 1257 #define FLD_PATH1_VOLUME 0x000000ff 1258 1259 /*****************************************************************************/ 1260 #define PATH1_EQ_CTL 0x8d8 1261 /* Reserved [31:30] */ 1262 #define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000 1263 /* Reserved [23:22] */ 1264 #define FLD_PATH1_EQ_MID_VOL 0x003f0000 1265 /* Reserved [15:14] */ 1266 #define FLD_PATH1_EQ_BASS_VOL 0x00003f00 1267 /* Reserved [7:1] */ 1268 #define FLD_PATH1_EQ_BAND_SEL 0x00000001 1269 1270 /*****************************************************************************/ 1271 #define PATH1_SC_CTL 0x8dc 1272 #define FLD_PATH1_SC_THRESHOLD 0x7fff0000 1273 #define FLD_PATH1_SC_RT 0x0000f000 1274 #define FLD_PATH1_SC_AT 0x00000f00 1275 #define FLD_PATH1_SC_STEREO 0x00000080 1276 #define FLD_PATH1_SC_CR 0x00000070 1277 #define FLD_PATH1_SC_RMS_CON 0x0000000f 1278 1279 /*****************************************************************************/ 1280 #define PATH2_CTL1 0x8e0 1281 /* Reserved [31:26] */ 1282 #define FLD_PATH2_MUTE_CTL 0x03000000 1283 /* Reserved [23:22] */ 1284 #define FLD_PATH2_AVC_CG 0x00300000 1285 #define FLD_PATH2_AVC_RT 0x000f0000 1286 #define FLD_PATH2_AVC_AT 0x0000f000 1287 #define FLD_PATH2_AVC_STEREO 0x00000800 1288 #define FLD_PATH2_AVC_CR 0x00000700 1289 #define FLD_PATH2_AVC_RMS_CON 0x000000f0 1290 #define FLD_PATH2_SEL_CTL 0x0000000f 1291 1292 /*****************************************************************************/ 1293 #define PATH2_VOL_CTL 0x8e4 1294 #define FLD_PATH2_AVC_THRESHOLD 0xffff0000 1295 #define FLD_PATH2_BAL_LEFT 0x00008000 1296 #define FLD_PATH2_BAL_LEVEL 0x00007f00 1297 #define FLD_PATH2_VOLUME 0x000000ff 1298 1299 /*****************************************************************************/ 1300 #define PATH2_EQ_CTL 0x8e8 1301 /* Reserved [31:30] */ 1302 #define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000 1303 /* Reserved [23:22] */ 1304 #define FLD_PATH2_EQ_MID_VOL 0x003f0000 1305 /* Reserved [15:14] */ 1306 #define FLD_PATH2_EQ_BASS_VOL 0x00003f00 1307 /* Reserved [7:1] */ 1308 #define FLD_PATH2_EQ_BAND_SEL 0x00000001 1309 1310 /*****************************************************************************/ 1311 #define PATH2_SC_CTL 0x8eC 1312 #define FLD_PATH2_SC_THRESHOLD 0xffff0000 1313 #define FLD_PATH2_SC_RT 0x0000f000 1314 #define FLD_PATH2_SC_AT 0x00000f00 1315 #define FLD_PATH2_SC_STEREO 0x00000080 1316 #define FLD_PATH2_SC_CR 0x00000070 1317 #define FLD_PATH2_SC_RMS_CON 0x0000000f 1318 1319 /*****************************************************************************/ 1320 #define SRC_CTL 0x8f0 1321 #define FLD_SRC_STATUS 0xffffff00 1322 #define FLD_FIFO_LF_EN 0x000000fc 1323 #define FLD_BYPASS_LI 0x00000002 1324 #define FLD_BYPASS_PF 0x00000001 1325 1326 /*****************************************************************************/ 1327 #define SRC_LF_COEF 0x8f4 1328 #define FLD_LOOP_FILTER_COEF2 0xffff0000 1329 #define FLD_LOOP_FILTER_COEF1 0x0000ffff 1330 1331 /*****************************************************************************/ 1332 #define SRC1_CTL 0x8f8 1333 /* Reserved [31:28] */ 1334 #define FLD_SRC1_FIFO_RD_TH 0x0f000000 1335 /* Reserved [23:18] */ 1336 #define FLD_SRC1_PHASE_INC 0x0003ffff 1337 1338 /*****************************************************************************/ 1339 #define SRC2_CTL 0x8fc 1340 /* Reserved [31:28] */ 1341 #define FLD_SRC2_FIFO_RD_TH 0x0f000000 1342 /* Reserved [23:18] */ 1343 #define FLD_SRC2_PHASE_INC 0x0003ffff 1344 1345 /*****************************************************************************/ 1346 #define SRC3_CTL 0x900 1347 /* Reserved [31:28] */ 1348 #define FLD_SRC3_FIFO_RD_TH 0x0f000000 1349 /* Reserved [23:18] */ 1350 #define FLD_SRC3_PHASE_INC 0x0003ffff 1351 1352 /*****************************************************************************/ 1353 #define SRC4_CTL 0x904 1354 /* Reserved [31:28] */ 1355 #define FLD_SRC4_FIFO_RD_TH 0x0f000000 1356 /* Reserved [23:18] */ 1357 #define FLD_SRC4_PHASE_INC 0x0003ffff 1358 1359 /*****************************************************************************/ 1360 #define SRC5_CTL 0x908 1361 /* Reserved [31:28] */ 1362 #define FLD_SRC5_FIFO_RD_TH 0x0f000000 1363 /* Reserved [23:18] */ 1364 #define FLD_SRC5_PHASE_INC 0x0003ffff 1365 1366 /*****************************************************************************/ 1367 #define SRC6_CTL 0x90c 1368 /* Reserved [31:28] */ 1369 #define FLD_SRC6_FIFO_RD_TH 0x0f000000 1370 /* Reserved [23:18] */ 1371 #define FLD_SRC6_PHASE_INC 0x0003ffff 1372 1373 /*****************************************************************************/ 1374 #define BAND_OUT_SEL 0x910 1375 #define FLD_SRC6_IN_SEL 0xc0000000 1376 #define FLD_SRC6_CLK_SEL 0x30000000 1377 #define FLD_SRC5_IN_SEL 0x0c000000 1378 #define FLD_SRC5_CLK_SEL 0x03000000 1379 #define FLD_SRC4_IN_SEL 0x00c00000 1380 #define FLD_SRC4_CLK_SEL 0x00300000 1381 #define FLD_SRC3_IN_SEL 0x000c0000 1382 #define FLD_SRC3_CLK_SEL 0x00030000 1383 #define FLD_BASEBAND_BYPASS_CTL 0x0000ff00 1384 #define FLD_AC97_SRC_SEL 0x000000c0 1385 #define FLD_I2S_SRC_SEL 0x00000030 1386 #define FLD_PARALLEL2_SRC_SEL 0x0000000c 1387 #define FLD_PARALLEL1_SRC_SEL 0x00000003 1388 1389 /*****************************************************************************/ 1390 #define I2S_IN_CTL 0x914 1391 /* Reserved [31:11] */ 1392 #define FLD_I2S_UP2X_BW20K 0x00000400 1393 #define FLD_I2S_UP2X_BYPASS 0x00000200 1394 #define FLD_I2S_IN_MASTER_MODE 0x00000100 1395 #define FLD_I2S_IN_SONY_MODE 0x00000080 1396 #define FLD_I2S_IN_RIGHT_JUST 0x00000040 1397 #define FLD_I2S_IN_WS_SEL 0x00000020 1398 #define FLD_I2S_IN_BCN_DEL 0x0000001f 1399 1400 /*****************************************************************************/ 1401 #define I2S_OUT_CTL 0x918 1402 /* Reserved [31:17] */ 1403 #define FLD_I2S_OUT_SOFT_RESET_EN 0x00010000 1404 /* Reserved [15:9] */ 1405 #define FLD_I2S_OUT_MASTER_MODE 0x00000100 1406 #define FLD_I2S_OUT_SONY_MODE 0x00000080 1407 #define FLD_I2S_OUT_RIGHT_JUST 0x00000040 1408 #define FLD_I2S_OUT_WS_SEL 0x00000020 1409 #define FLD_I2S_OUT_BCN_DEL 0x0000001f 1410 1411 /*****************************************************************************/ 1412 #define AC97_CTL 0x91c 1413 /* Reserved [31:26] */ 1414 #define FLD_AC97_UP2X_BW20K 0x02000000 1415 #define FLD_AC97_UP2X_BYPASS 0x01000000 1416 /* Reserved [23:17] */ 1417 #define FLD_AC97_RST_ACL 0x00010000 1418 /* Reserved [15:9] */ 1419 #define FLD_AC97_WAKE_UP_SYNC 0x00000100 1420 /* Reserved [7:1] */ 1421 #define FLD_AC97_SHUTDOWN 0x00000001 1422 1423 /* Cx231xx redefine */ 1424 #define QPSK_IAGC_CTL1 0x94c 1425 #define QPSK_IAGC_CTL2 0x950 1426 #define QPSK_FEPR_FREQ 0x954 1427 #define QPSK_BTL_CTL1 0x958 1428 #define QPSK_BTL_CTL2 0x95c 1429 #define QPSK_CTL_CTL1 0x960 1430 #define QPSK_CTL_CTL2 0x964 1431 #define QPSK_MF_FAGC_CTL 0x968 1432 #define QPSK_EQ_CTL 0x96c 1433 #define QPSK_LOCK_CTL 0x970 1434 1435 /*****************************************************************************/ 1436 #define FM1_DFT_CTL 0x9a8 1437 #define FLD_FM1_DFT_THRESHOLD 0xffff0000 1438 /* Reserved [15:8] */ 1439 #define FLD_FM1_DFT_CMP_CTL 0x00000080 1440 #define FLD_FM1_DFT_AVG 0x00000070 1441 /* Reserved [3:1] */ 1442 #define FLD_FM1_DFT_START 0x00000001 1443 1444 /*****************************************************************************/ 1445 #define FM1_DFT_STATUS 0x9ac 1446 #define FLD_FM1_DFT_DONE 0x80000000 1447 /* Reserved [30:19] */ 1448 #define FLD_FM_DFT_TH_CMP 0x00040000 1449 #define FLD_FM1_DFT 0x0003ffff 1450 1451 /*****************************************************************************/ 1452 #define FM2_DFT_CTL 0x9b0 1453 #define FLD_FM2_DFT_THRESHOLD 0xffff0000 1454 /* Reserved [15:8] */ 1455 #define FLD_FM2_DFT_CMP_CTL 0x00000080 1456 #define FLD_FM2_DFT_AVG 0x00000070 1457 /* Reserved [3:1] */ 1458 #define FLD_FM2_DFT_START 0x00000001 1459 1460 /*****************************************************************************/ 1461 #define FM2_DFT_STATUS 0x9b4 1462 #define FLD_FM2_DFT_DONE 0x80000000 1463 /* Reserved [30:19] */ 1464 #define FLD_FM2_DFT_TH_CMP_STAT 0x00040000 1465 #define FLD_FM2_DFT 0x0003ffff 1466 1467 /*****************************************************************************/ 1468 /* Cx231xx redefine */ 1469 #define AAGC_STATUS_REG 0x9b8 1470 #define AAGC_STATUS 0x9b8 1471 /* Reserved [31:27] */ 1472 #define FLD_FM2_DAGC_OUT 0x07000000 1473 /* Reserved [23:19] */ 1474 #define FLD_FM1_DAGC_OUT 0x00070000 1475 /* Reserved [15:6] */ 1476 #define FLD_AFE_VGA_OUT 0x0000003f 1477 1478 /*****************************************************************************/ 1479 #define MTS_GAIN_STATUS 0x9bc 1480 /* Reserved [31:14] */ 1481 #define FLD_MTS_GAIN 0x00003fff 1482 1483 #define RDS_OUT 0x9c0 1484 #define FLD_RDS_Q 0xffff0000 1485 #define FLD_RDS_I 0x0000ffff 1486 1487 /*****************************************************************************/ 1488 #define AUTOCONFIG_REG 0x9c4 1489 /* Reserved [31:4] */ 1490 #define FLD_AUTOCONFIG_MODE 0x0000000f 1491 1492 #define FM_AFC 0x9c8 1493 #define FLD_FM2_AFC 0xffff0000 1494 #define FLD_FM1_AFC 0x0000ffff 1495 1496 /*****************************************************************************/ 1497 /* Cx231xx redefine */ 1498 #define NEW_SPARE 0x9cc 1499 #define NEW_SPARE_REG 0x9cc 1500 1501 /*****************************************************************************/ 1502 #define DBX_ADJ 0x9d0 1503 /* Reserved [31:28] */ 1504 #define FLD_DBX2_ADJ 0x0fff0000 1505 /* Reserved [15:12] */ 1506 #define FLD_DBX1_ADJ 0x00000fff 1507 1508 #define VID_FMT_AUTO 0 1509 #define VID_FMT_NTSC_M 1 1510 #define VID_FMT_NTSC_J 2 1511 #define VID_FMT_NTSC_443 3 1512 #define VID_FMT_PAL_BDGHI 4 1513 #define VID_FMT_PAL_M 5 1514 #define VID_FMT_PAL_N 6 1515 #define VID_FMT_PAL_NC 7 1516 #define VID_FMT_PAL_60 8 1517 #define VID_FMT_SECAM 12 1518 #define VID_FMT_SECAM_60 13 1519 1520 #define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ 1521 #define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ 1522 #define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ 1523 #define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ 1524 1525 #define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ 1526 #define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ 1527 #define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ 1528 1529 #define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ 1530 #define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ 1531 #define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ 1532 1533 #define TWO_TAP_FILT 0 1534 #define THREE_TAP_FILT 1 1535 #define FOUR_TAP_FILT 2 1536 #define FIVE_TAP_FILT 3 1537 1538 #define AUD_CHAN_SRC_PARALLEL 0 1539 #define AUD_CHAN_SRC_I2S_INPUT 1 1540 #define AUD_CHAN_SRC_FLATIRON 2 1541 #define AUD_CHAN_SRC_PARALLEL3 3 1542 1543 #define OUT_MODE_601 0 1544 #define OUT_MODE_656 1 1545 #define OUT_MODE_VIP11 2 1546 #define OUT_MODE_VIP20 3 1547 1548 #define PHASE_INC_49MHZ 0x0df22 1549 #define PHASE_INC_56MHZ 0x0fa5b 1550 #define PHASE_INC_28MHZ 0x010000 1551 1552 #endif 1553
