Searched refs:Divider (Results 1 – 23 of 23) sorted by relevance
1 * Core Divider Clock bindings for Marvell MVEBU SoCs12 - reg : must be the register address of Core Divider control register
18 - reg : shall be the register address of the Core PLL and Clock Divider20 Core PLL and Clock Divider Control 1 register. Thus, it will have
162 uint8_t Divider; member
258 uint8_t Divider; member
917 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()980 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()1039 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
2699 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()2732 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()2764 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
205 uint8_t Divider; member
187 uint8_t Divider; member
179 uint8_t Divider; member
198 uint8_t Divider; member
213 uint8_t Divider; member
36 4: N-Divider output
189 int Multiplier, Divider, Remainder; in ATIReduceRatio() local192 Divider = *Denominator; in ATIReduceRatio()194 while ((Remainder = Multiplier % Divider)) { in ATIReduceRatio()195 Multiplier = Divider; in ATIReduceRatio()196 Divider = Remainder; in ATIReduceRatio()199 *Numerator /= Divider; in ATIReduceRatio()200 *Denominator /= Divider; in ATIReduceRatio()
96 Voltage R1 R2 Divider Raw Value
1000 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()1063 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()1122 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1450 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_vce_level()1486 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_acp_level()
1582 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_vce_level()1612 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acp_level()
1405 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_vce_level()1449 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_acp_level()
1237 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_vce_level()
1329 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_vce_level()
231 bit 6-4 = Divider for clock
