1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #ifndef __ETH_COMMON__ 8 #define __ETH_COMMON__ 9 10 /********************/ 11 /* ETH FW CONSTANTS */ 12 /********************/ 13 14 #define ETH_HSI_VER_MAJOR 3 15 #define ETH_HSI_VER_MINOR 11 16 17 #define ETH_HSI_VER_NO_PKT_LEN_TUNN 5 18 /* Maximum number of pinned L2 connections (CIDs) */ 19 #define ETH_PINNED_CONN_MAX_NUM 32 20 21 #define ETH_CACHE_LINE_SIZE 64 22 #define ETH_RX_CQE_GAP 32 23 #define ETH_MAX_RAMROD_PER_CON 8 24 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096 25 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096 26 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 27 #define ETH_RX_NUM_NEXT_PAGE_BDS 2 28 29 #define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253 30 #define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251 31 32 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 33 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 34 #define ETH_TX_MAX_BDS_PER_LSO_PACKET 255 35 #define ETH_TX_MAX_LSO_HDR_NBD 4 36 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3 37 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 38 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 39 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 40 #define ETH_TX_MIN_BDS_PER_PKT_W_VPORT_FORWARDING 4 41 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8)) 42 #define ETH_TX_MAX_LSO_HDR_BYTES 510 43 #define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1) 44 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700 45 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000 46 #define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320 47 #define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF 48 49 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 50 #define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \ 51 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2) 52 #define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \ 53 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4) 54 55 #define ETH_RX_MAX_BUFF_PER_PKT 5 56 #define ETH_RX_BD_THRESHOLD 16 57 58 /* Num of MAC/VLAN filters */ 59 #define ETH_NUM_MAC_FILTERS 512 60 #define ETH_NUM_VLAN_FILTERS 512 61 62 /* Approx. multicast constants */ 63 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 64 #define ETH_MULTICAST_MAC_BINS 256 65 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) 66 67 /* Ethernet vport update constants */ 68 #define ETH_FILTER_RULES_COUNT 10 69 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 70 #define ETH_RSS_KEY_SIZE_REGS 10 71 #define ETH_RSS_ENGINE_NUM_K2 207 72 #define ETH_RSS_ENGINE_NUM_BB 127 73 74 /* TPA constants */ 75 #define ETH_TPA_MAX_AGGS_NUM 64 76 #define ETH_TPA_CQE_START_BW_LEN_LIST_SIZE 2 77 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6 78 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4 79 80 /* Control frame check constants */ 81 #define ETH_CTL_FRAME_ETH_TYPE_NUM 4 82 83 /* GFS constants */ 84 #define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */ 85 86 /* Destination port mode */ 87 enum dst_port_mode { 88 DST_PORT_PHY, 89 DST_PORT_LOOPBACK, 90 DST_PORT_PHY_LOOPBACK, 91 DST_PORT_DROP, 92 MAX_DST_PORT_MODE 93 }; 94 95 /* Ethernet address type */ 96 enum eth_addr_type { 97 BROADCAST_ADDRESS, 98 MULTICAST_ADDRESS, 99 UNICAST_ADDRESS, 100 UNKNOWN_ADDRESS, 101 MAX_ETH_ADDR_TYPE 102 }; 103 104 struct eth_tx_1st_bd_flags { 105 u8 bitfields; 106 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 107 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0 108 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 109 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1 110 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 111 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2 112 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 113 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3 114 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 115 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4 116 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1 117 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5 118 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1 119 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 120 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 121 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 122 }; 123 124 /* The parsing information data fo rthe first tx bd of a given packet */ 125 struct eth_tx_data_1st_bd { 126 __le16 vlan; 127 u8 nbds; 128 struct eth_tx_1st_bd_flags bd_flags; 129 __le16 bitfields; 130 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1 131 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0 132 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 133 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 134 #define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF 135 #define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2 136 }; 137 138 /* The parsing information data for the second tx bd of a given packet */ 139 struct eth_tx_data_2nd_bd { 140 __le16 tunn_ip_size; 141 __le16 bitfields1; 142 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF 143 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0 144 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3 145 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4 146 #define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_MASK 0x3 147 #define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_SHIFT 6 148 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1 149 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8 150 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3 151 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9 152 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1 153 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11 154 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1 155 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12 156 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1 157 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13 158 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1 159 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14 160 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1 161 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15 162 __le16 bitfields2; 163 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF 164 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0 165 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7 166 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13 167 }; 168 169 /* Firmware data for L2-EDPM packet */ 170 struct eth_edpm_fw_data { 171 struct eth_tx_data_1st_bd data_1st_bd; 172 struct eth_tx_data_2nd_bd data_2nd_bd; 173 __le32 reserved; 174 }; 175 176 /* Tunneling parsing flags */ 177 struct eth_tunnel_parsing_flags { 178 u8 flags; 179 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3 180 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0 181 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1 182 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2 183 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3 184 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3 185 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1 186 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5 187 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1 188 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6 189 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1 190 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7 191 }; 192 193 /* PMD flow control bits */ 194 struct eth_pmd_flow_flags { 195 u8 flags; 196 #define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1 197 #define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0 198 #define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1 199 #define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1 200 #define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F 201 #define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2 202 }; 203 204 /* Regular ETH Rx FP CQE */ 205 struct eth_fast_path_rx_reg_cqe { 206 u8 type; 207 u8 bitfields; 208 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7 209 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0 210 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF 211 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3 212 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1 213 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7 214 __le16 pkt_len; 215 struct parsing_and_err_flags pars_flags; 216 __le16 vlan_tag; 217 __le32 rss_hash; 218 __le16 len_on_first_bd; 219 u8 placement_offset; 220 struct eth_tunnel_parsing_flags tunnel_pars_flags; 221 u8 bd_num; 222 u8 reserved; 223 __le16 reserved2; 224 __le32 flow_id_or_resource_id; 225 u8 reserved1[7]; 226 struct eth_pmd_flow_flags pmd_flags; 227 }; 228 229 /* TPA-continue ETH Rx FP CQE */ 230 struct eth_fast_path_rx_tpa_cont_cqe { 231 u8 type; 232 u8 tpa_agg_index; 233 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 234 u8 reserved; 235 u8 reserved1; 236 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 237 u8 reserved3[3]; 238 struct eth_pmd_flow_flags pmd_flags; 239 }; 240 241 /* TPA-end ETH Rx FP CQE */ 242 struct eth_fast_path_rx_tpa_end_cqe { 243 u8 type; 244 u8 tpa_agg_index; 245 __le16 total_packet_len; 246 u8 num_of_bds; 247 u8 end_reason; 248 __le16 num_of_coalesced_segs; 249 __le32 ts_delta; 250 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 251 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 252 __le16 reserved1; 253 u8 reserved2; 254 struct eth_pmd_flow_flags pmd_flags; 255 }; 256 257 /* TPA-start ETH Rx FP CQE */ 258 struct eth_fast_path_rx_tpa_start_cqe { 259 u8 type; 260 u8 bitfields; 261 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7 262 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0 263 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF 264 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3 265 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1 266 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7 267 __le16 seg_len; 268 struct parsing_and_err_flags pars_flags; 269 __le16 vlan_tag; 270 __le32 rss_hash; 271 __le16 len_on_first_bd; 272 u8 placement_offset; 273 struct eth_tunnel_parsing_flags tunnel_pars_flags; 274 u8 tpa_agg_index; 275 u8 header_len; 276 __le16 bw_ext_bd_len_list[ETH_TPA_CQE_START_BW_LEN_LIST_SIZE]; 277 __le16 reserved2; 278 __le32 flow_id_or_resource_id; 279 u8 reserved[3]; 280 struct eth_pmd_flow_flags pmd_flags; 281 }; 282 283 /* The L4 pseudo checksum mode for Ethernet */ 284 enum eth_l4_pseudo_checksum_mode { 285 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH, 286 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH, 287 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE 288 }; 289 290 struct eth_rx_bd { 291 struct regpair addr; 292 }; 293 294 /* Regular ETH Rx SP CQE */ 295 struct eth_slow_path_rx_cqe { 296 u8 type; 297 u8 ramrod_cmd_id; 298 u8 error_flag; 299 u8 reserved[25]; 300 __le16 echo; 301 u8 reserved1; 302 struct eth_pmd_flow_flags pmd_flags; 303 }; 304 305 /* Union for all ETH Rx CQE types */ 306 union eth_rx_cqe { 307 struct eth_fast_path_rx_reg_cqe fast_path_regular; 308 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start; 309 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont; 310 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end; 311 struct eth_slow_path_rx_cqe slow_path; 312 }; 313 314 /* ETH Rx CQE type */ 315 enum eth_rx_cqe_type { 316 ETH_RX_CQE_TYPE_UNUSED, 317 ETH_RX_CQE_TYPE_REGULAR, 318 ETH_RX_CQE_TYPE_SLOW_PATH, 319 ETH_RX_CQE_TYPE_TPA_START, 320 ETH_RX_CQE_TYPE_TPA_CONT, 321 ETH_RX_CQE_TYPE_TPA_END, 322 MAX_ETH_RX_CQE_TYPE 323 }; 324 325 struct eth_rx_pmd_cqe { 326 union eth_rx_cqe cqe; 327 u8 reserved[ETH_RX_CQE_GAP]; 328 }; 329 330 enum eth_rx_tunn_type { 331 ETH_RX_NO_TUNN, 332 ETH_RX_TUNN_GENEVE, 333 ETH_RX_TUNN_GRE, 334 ETH_RX_TUNN_VXLAN, 335 MAX_ETH_RX_TUNN_TYPE 336 }; 337 338 /* Aggregation end reason. */ 339 enum eth_tpa_end_reason { 340 ETH_AGG_END_UNUSED, 341 ETH_AGG_END_SP_UPDATE, 342 ETH_AGG_END_MAX_LEN, 343 ETH_AGG_END_LAST_SEG, 344 ETH_AGG_END_TIMEOUT, 345 ETH_AGG_END_NOT_CONSISTENT, 346 ETH_AGG_END_OUT_OF_ORDER, 347 ETH_AGG_END_NON_TPA_SEG, 348 MAX_ETH_TPA_END_REASON 349 }; 350 351 /* The first tx bd of a given packet */ 352 struct eth_tx_1st_bd { 353 struct regpair addr; 354 __le16 nbytes; 355 struct eth_tx_data_1st_bd data; 356 }; 357 358 /* The second tx bd of a given packet */ 359 struct eth_tx_2nd_bd { 360 struct regpair addr; 361 __le16 nbytes; 362 struct eth_tx_data_2nd_bd data; 363 }; 364 365 /* The parsing information data for the third tx bd of a given packet */ 366 struct eth_tx_data_3rd_bd { 367 __le16 lso_mss; 368 __le16 bitfields; 369 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF 370 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0 371 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF 372 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4 373 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1 374 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8 375 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F 376 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9 377 u8 tunn_l4_hdr_start_offset_w; 378 u8 tunn_hdr_size_w; 379 }; 380 381 /* The third tx bd of a given packet */ 382 struct eth_tx_3rd_bd { 383 struct regpair addr; 384 __le16 nbytes; 385 struct eth_tx_data_3rd_bd data; 386 }; 387 388 /* The parsing information data for the forth tx bd of a given packet. */ 389 struct eth_tx_data_4th_bd { 390 u8 dst_vport_id; 391 u8 reserved4; 392 __le16 bitfields; 393 #define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_MASK 0x1 394 #define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_SHIFT 0 395 #define ETH_TX_DATA_4TH_BD_RESERVED1_MASK 0x7F 396 #define ETH_TX_DATA_4TH_BD_RESERVED1_SHIFT 1 397 #define ETH_TX_DATA_4TH_BD_START_BD_MASK 0x1 398 #define ETH_TX_DATA_4TH_BD_START_BD_SHIFT 8 399 #define ETH_TX_DATA_4TH_BD_RESERVED2_MASK 0x7F 400 #define ETH_TX_DATA_4TH_BD_RESERVED2_SHIFT 9 401 __le16 reserved3; 402 }; 403 404 /* The forth tx bd of a given packet */ 405 struct eth_tx_4th_bd { 406 struct regpair addr; /* Single continuous buffer */ 407 __le16 nbytes; /* Number of bytes in this BD */ 408 struct eth_tx_data_4th_bd data; /* Parsing information data */ 409 }; 410 411 /* Complementary information for the regular tx bd of a given packet */ 412 struct eth_tx_data_bd { 413 __le16 reserved0; 414 __le16 bitfields; 415 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF 416 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0 417 #define ETH_TX_DATA_BD_START_BD_MASK 0x1 418 #define ETH_TX_DATA_BD_START_BD_SHIFT 8 419 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F 420 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9 421 __le16 reserved3; 422 }; 423 424 /* The common non-special TX BD ring element */ 425 struct eth_tx_bd { 426 struct regpair addr; 427 __le16 nbytes; 428 struct eth_tx_data_bd data; 429 }; 430 431 union eth_tx_bd_types { 432 struct eth_tx_1st_bd first_bd; 433 struct eth_tx_2nd_bd second_bd; 434 struct eth_tx_3rd_bd third_bd; 435 struct eth_tx_4th_bd fourth_bd; 436 struct eth_tx_bd reg_bd; 437 }; 438 439 /* Mstorm Queue Zone */ 440 enum eth_tx_tunn_type { 441 ETH_TX_TUNN_GENEVE, 442 ETH_TX_TUNN_TTAG, 443 ETH_TX_TUNN_GRE, 444 ETH_TX_TUNN_VXLAN, 445 MAX_ETH_TX_TUNN_TYPE 446 }; 447 448 /* Mstorm Queue Zone */ 449 struct mstorm_eth_queue_zone { 450 struct eth_rx_prod_data rx_producers; 451 __le32 reserved[3]; 452 }; 453 454 /* Ystorm Queue Zone */ 455 struct xstorm_eth_queue_zone { 456 struct coalescing_timeset int_coalescing_timeset; 457 u8 reserved[7]; 458 }; 459 460 /* ETH doorbell data */ 461 struct eth_db_data { 462 u8 params; 463 #define ETH_DB_DATA_DEST_MASK 0x3 464 #define ETH_DB_DATA_DEST_SHIFT 0 465 #define ETH_DB_DATA_AGG_CMD_MASK 0x3 466 #define ETH_DB_DATA_AGG_CMD_SHIFT 2 467 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1 468 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4 469 #define ETH_DB_DATA_RESERVED_MASK 0x1 470 #define ETH_DB_DATA_RESERVED_SHIFT 5 471 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3 472 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6 473 u8 agg_flags; 474 __le16 bd_prod; 475 }; 476 477 /* RSS hash type */ 478 enum rss_hash_type { 479 RSS_HASH_TYPE_DEFAULT = 0, 480 RSS_HASH_TYPE_IPV4 = 1, 481 RSS_HASH_TYPE_TCP_IPV4 = 2, 482 RSS_HASH_TYPE_IPV6 = 3, 483 RSS_HASH_TYPE_TCP_IPV6 = 4, 484 RSS_HASH_TYPE_UDP_IPV4 = 5, 485 RSS_HASH_TYPE_UDP_IPV6 = 6, 486 MAX_RSS_HASH_TYPE 487 }; 488 489 #endif /* __ETH_COMMON__ */ 490
