Searched refs:DP_TRAIN_PRE_EMPHASIS_MASK (Results 1 – 9 of 9) sorted by relevance
231 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); in amdgpu_atombios_dp_get_adjust_train()658 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()711 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in amdgpu_atombios_dp_link_train_ce()
287 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); in dp_get_adjust_train()726 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()777 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in radeon_dp_link_train_ce()
39 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { in dp_voltage_max()
4167 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()4251 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()4344 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in g4x_signal_levels()4385 DP_TRAIN_PRE_EMPHASIS_MASK); in snb_cpu_edp_signal_levels()4432 DP_TRAIN_PRE_EMPHASIS_MASK); in ivb_cpu_edp_signal_levels()4488 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> in intel_dp_set_signal_levels()
2822 DP_TRAIN_PRE_EMPHASIS_MASK); in intel_ddi_dp_level()
1298 if (p == DP_TRAIN_PRE_EMPHASIS_MASK) in cdv_intel_get_adjust_train()1418 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >> in cdv_intel_dp_set_vswing_premph()
478 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) macro
672 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) in zynqmp_dp_update_vs_emph()
1135 same_pre = (before_cr[i] & DP_TRAIN_PRE_EMPHASIS_MASK) == in cdns_mhdp_validate_cr()
