Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 7 of 7) sorted by relevance
226 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()662 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()725 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
523 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
232 #define DPLL_VGA_MODE_DIS (1 << 28) macro
1495 DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_disable_pll()1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()8398 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_compute_dpll()8415 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_compute_dpll()8696 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()8770 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()18084 DPLL_VGA_MODE_DIS | in i830_enable_pipe()[all …]
1406 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
3427 #define DPLL_VGA_MODE_DIS (1 << 28) macro
