Searched refs:DMA_CHAN_TX_CONTROL (Results 1 – 3 of 3) sorted by relevance
96 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()102 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()154 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = in _dwmac4_dump_dma_regs()155 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); in _dwmac4_dump_dma_regs()425 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()427 ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()430 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()432 ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()477 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tbs()484 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tbs()[all …]
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()43 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()52 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()55 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
99 #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) macro
