Searched refs:DMA_CHAN_INTR_ENA (Results 1 – 3 of 3) sorted by relevance
95 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()102 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()107 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()114 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()119 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()126 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()131 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()138 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()145 u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_dma_interrupt()
124 ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_dma_init_channel()170 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = in _dwmac4_dump_dma_regs()171 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); in _dwmac4_dump_dma_regs()
109 #define DMA_CHAN_INTR_ENA(x) (DMA_CHANX_BASE_ADDR(x) + 0x34) macro
