1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014-2020 Broadcom 4 */ 5 6 #ifndef __BCMGENET_H__ 7 #define __BCMGENET_H__ 8 9 #include <linux/skbuff.h> 10 #include <linux/netdevice.h> 11 #include <linux/spinlock.h> 12 #include <linux/clk.h> 13 #include <linux/mii.h> 14 #include <linux/if_vlan.h> 15 #include <linux/phy.h> 16 #include <linux/dim.h> 17 #include <linux/ethtool.h> 18 19 /* total number of Buffer Descriptors, same for Rx/Tx */ 20 #define TOTAL_DESC 256 21 22 /* which ring is descriptor based */ 23 #define DESC_INDEX 16 24 25 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 26 * 1536 is multiple of 256 bytes 27 */ 28 #define ENET_BRCM_TAG_LEN 6 29 #define ENET_PAD 8 30 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 31 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 32 #define DMA_MAX_BURST_LENGTH 0x10 33 34 /* misc. configuration */ 35 #define MAX_NUM_OF_FS_RULES 16 36 #define CLEAR_ALL_HFB 0xFF 37 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 38 #define DMA_FC_THRESH_LO 5 39 40 /* 64B receive/transmit status block */ 41 struct status_64 { 42 u32 length_status; /* length and peripheral status */ 43 u32 ext_status; /* Extended status*/ 44 u32 rx_csum; /* partial rx checksum */ 45 u32 unused1[9]; /* unused */ 46 u32 tx_csum_info; /* Tx checksum info. */ 47 u32 unused2[3]; /* unused */ 48 }; 49 50 /* Rx status bits */ 51 #define STATUS_RX_EXT_MASK 0x1FFFFF 52 #define STATUS_RX_CSUM_MASK 0xFFFF 53 #define STATUS_RX_CSUM_OK 0x10000 54 #define STATUS_RX_CSUM_FR 0x20000 55 #define STATUS_RX_PROTO_TCP 0 56 #define STATUS_RX_PROTO_UDP 1 57 #define STATUS_RX_PROTO_ICMP 2 58 #define STATUS_RX_PROTO_OTHER 3 59 #define STATUS_RX_PROTO_MASK 3 60 #define STATUS_RX_PROTO_SHIFT 18 61 #define STATUS_FILTER_INDEX_MASK 0xFFFF 62 /* Tx status bits */ 63 #define STATUS_TX_CSUM_START_MASK 0X7FFF 64 #define STATUS_TX_CSUM_START_SHIFT 16 65 #define STATUS_TX_CSUM_PROTO_UDP 0x8000 66 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 67 #define STATUS_TX_CSUM_LV 0x80000000 68 69 /* DMA Descriptor */ 70 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 71 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 72 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 73 74 /* Rx/Tx common counter group */ 75 struct bcmgenet_pkt_counters { 76 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 77 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 78 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 79 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 80 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 81 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 82 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 83 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 84 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 85 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 86 }; 87 88 /* RSV, Receive Status Vector */ 89 struct bcmgenet_rx_counters { 90 struct bcmgenet_pkt_counters pkt_cnt; 91 u32 pkt; /* RO (0x428) Received pkt count*/ 92 u32 bytes; /* RO Received byte count */ 93 u32 mca; /* RO # of Received multicast pkt */ 94 u32 bca; /* RO # of Receive broadcast pkt */ 95 u32 fcs; /* RO # of Received FCS error */ 96 u32 cf; /* RO # of Received control frame pkt*/ 97 u32 pf; /* RO # of Received pause frame pkt */ 98 u32 uo; /* RO # of unknown op code pkt */ 99 u32 aln; /* RO # of alignment error count */ 100 u32 flr; /* RO # of frame length out of range count */ 101 u32 cde; /* RO # of code error pkt */ 102 u32 fcr; /* RO # of carrier sense error pkt */ 103 u32 ovr; /* RO # of oversize pkt*/ 104 u32 jbr; /* RO # of jabber count */ 105 u32 mtue; /* RO # of MTU error pkt*/ 106 u32 pok; /* RO # of Received good pkt */ 107 u32 uc; /* RO # of unicast pkt */ 108 u32 ppp; /* RO # of PPP pkt */ 109 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 110 }; 111 112 /* TSV, Transmit Status Vector */ 113 struct bcmgenet_tx_counters { 114 struct bcmgenet_pkt_counters pkt_cnt; 115 u32 pkts; /* RO (0x4a8) Transmited pkt */ 116 u32 mca; /* RO # of xmited multicast pkt */ 117 u32 bca; /* RO # of xmited broadcast pkt */ 118 u32 pf; /* RO # of xmited pause frame count */ 119 u32 cf; /* RO # of xmited control frame count */ 120 u32 fcs; /* RO # of xmited FCS error count */ 121 u32 ovr; /* RO # of xmited oversize pkt */ 122 u32 drf; /* RO # of xmited deferral pkt */ 123 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 124 u32 scl; /* RO # of xmited single collision pkt */ 125 u32 mcl; /* RO # of xmited multiple collision pkt*/ 126 u32 lcl; /* RO # of xmited late collision pkt */ 127 u32 ecl; /* RO # of xmited excessive collision pkt*/ 128 u32 frg; /* RO # of xmited fragments pkt*/ 129 u32 ncl; /* RO # of xmited total collision count */ 130 u32 jbr; /* RO # of xmited jabber count*/ 131 u32 bytes; /* RO # of xmited byte count */ 132 u32 pok; /* RO # of xmited good pkt */ 133 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 134 }; 135 136 struct bcmgenet_mib_counters { 137 struct bcmgenet_rx_counters rx; 138 struct bcmgenet_tx_counters tx; 139 u32 rx_runt_cnt; 140 u32 rx_runt_fcs; 141 u32 rx_runt_fcs_align; 142 u32 rx_runt_bytes; 143 u32 rbuf_ovflow_cnt; 144 u32 rbuf_err_cnt; 145 u32 mdf_err_cnt; 146 u32 alloc_rx_buff_failed; 147 u32 rx_dma_failed; 148 u32 tx_dma_failed; 149 u32 tx_realloc_tsb; 150 u32 tx_realloc_tsb_failed; 151 }; 152 153 #define UMAC_HD_BKP_CTRL 0x004 154 #define HD_FC_EN (1 << 0) 155 #define HD_FC_BKOFF_OK (1 << 1) 156 #define IPG_CONFIG_RX_SHIFT 2 157 #define IPG_CONFIG_RX_MASK 0x1F 158 159 #define UMAC_CMD 0x008 160 #define CMD_TX_EN (1 << 0) 161 #define CMD_RX_EN (1 << 1) 162 #define UMAC_SPEED_10 0 163 #define UMAC_SPEED_100 1 164 #define UMAC_SPEED_1000 2 165 #define UMAC_SPEED_2500 3 166 #define CMD_SPEED_SHIFT 2 167 #define CMD_SPEED_MASK 3 168 #define CMD_PROMISC (1 << 4) 169 #define CMD_PAD_EN (1 << 5) 170 #define CMD_CRC_FWD (1 << 6) 171 #define CMD_PAUSE_FWD (1 << 7) 172 #define CMD_RX_PAUSE_IGNORE (1 << 8) 173 #define CMD_TX_ADDR_INS (1 << 9) 174 #define CMD_HD_EN (1 << 10) 175 #define CMD_SW_RESET (1 << 13) 176 #define CMD_LCL_LOOP_EN (1 << 15) 177 #define CMD_AUTO_CONFIG (1 << 22) 178 #define CMD_CNTL_FRM_EN (1 << 23) 179 #define CMD_NO_LEN_CHK (1 << 24) 180 #define CMD_RMT_LOOP_EN (1 << 25) 181 #define CMD_PRBL_EN (1 << 27) 182 #define CMD_TX_PAUSE_IGNORE (1 << 28) 183 #define CMD_TX_RX_EN (1 << 29) 184 #define CMD_RUNT_FILTER_DIS (1 << 30) 185 186 #define UMAC_MAC0 0x00C 187 #define UMAC_MAC1 0x010 188 #define UMAC_MAX_FRAME_LEN 0x014 189 190 #define UMAC_MODE 0x44 191 #define MODE_LINK_STATUS (1 << 5) 192 193 #define UMAC_EEE_CTRL 0x064 194 #define EN_LPI_RX_PAUSE (1 << 0) 195 #define EN_LPI_TX_PFC (1 << 1) 196 #define EN_LPI_TX_PAUSE (1 << 2) 197 #define EEE_EN (1 << 3) 198 #define RX_FIFO_CHECK (1 << 4) 199 #define EEE_TX_CLK_DIS (1 << 5) 200 #define DIS_EEE_10M (1 << 6) 201 #define LP_IDLE_PREDICTION_MODE (1 << 7) 202 203 #define UMAC_EEE_LPI_TIMER 0x068 204 #define UMAC_EEE_WAKE_TIMER 0x06C 205 #define UMAC_EEE_REF_COUNT 0x070 206 #define EEE_REFERENCE_COUNT_MASK 0xffff 207 208 #define UMAC_TX_FLUSH 0x334 209 210 #define UMAC_MIB_START 0x400 211 212 #define UMAC_MDIO_CMD 0x614 213 #define MDIO_START_BUSY (1 << 29) 214 #define MDIO_READ_FAIL (1 << 28) 215 #define MDIO_RD (2 << 26) 216 #define MDIO_WR (1 << 26) 217 #define MDIO_PMD_SHIFT 21 218 #define MDIO_PMD_MASK 0x1F 219 #define MDIO_REG_SHIFT 16 220 #define MDIO_REG_MASK 0x1F 221 222 #define UMAC_RBUF_OVFL_CNT_V1 0x61C 223 #define RBUF_OVFL_CNT_V2 0x80 224 #define RBUF_OVFL_CNT_V3PLUS 0x94 225 226 #define UMAC_MPD_CTRL 0x620 227 #define MPD_EN (1 << 0) 228 #define MPD_PW_EN (1 << 27) 229 #define MPD_MSEQ_LEN_SHIFT 16 230 #define MPD_MSEQ_LEN_MASK 0xFF 231 232 #define UMAC_MPD_PW_MS 0x624 233 #define UMAC_MPD_PW_LS 0x628 234 #define UMAC_RBUF_ERR_CNT_V1 0x634 235 #define RBUF_ERR_CNT_V2 0x84 236 #define RBUF_ERR_CNT_V3PLUS 0x98 237 #define UMAC_MDF_ERR_CNT 0x638 238 #define UMAC_MDF_CTRL 0x650 239 #define UMAC_MDF_ADDR 0x654 240 #define UMAC_MIB_CTRL 0x580 241 #define MIB_RESET_RX (1 << 0) 242 #define MIB_RESET_RUNT (1 << 1) 243 #define MIB_RESET_TX (1 << 2) 244 245 #define RBUF_CTRL 0x00 246 #define RBUF_64B_EN (1 << 0) 247 #define RBUF_ALIGN_2B (1 << 1) 248 #define RBUF_BAD_DIS (1 << 2) 249 250 #define RBUF_STATUS 0x0C 251 #define RBUF_STATUS_WOL (1 << 0) 252 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 253 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 254 255 #define RBUF_CHK_CTRL 0x14 256 #define RBUF_RXCHK_EN (1 << 0) 257 #define RBUF_SKIP_FCS (1 << 4) 258 #define RBUF_L3_PARSE_DIS (1 << 5) 259 260 #define RBUF_ENERGY_CTRL 0x9c 261 #define RBUF_EEE_EN (1 << 0) 262 #define RBUF_PM_EN (1 << 1) 263 264 #define RBUF_TBUF_SIZE_CTRL 0xb4 265 266 #define RBUF_HFB_CTRL_V1 0x38 267 #define RBUF_HFB_FILTER_EN_SHIFT 16 268 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 269 #define RBUF_HFB_EN (1 << 0) 270 #define RBUF_HFB_256B (1 << 1) 271 #define RBUF_ACPI_EN (1 << 2) 272 273 #define RBUF_HFB_LEN_V1 0x3C 274 #define RBUF_FLTR_LEN_MASK 0xFF 275 #define RBUF_FLTR_LEN_SHIFT 8 276 277 #define TBUF_CTRL 0x00 278 #define TBUF_64B_EN (1 << 0) 279 #define TBUF_BP_MC 0x0C 280 #define TBUF_ENERGY_CTRL 0x14 281 #define TBUF_EEE_EN (1 << 0) 282 #define TBUF_PM_EN (1 << 1) 283 284 #define TBUF_CTRL_V1 0x80 285 #define TBUF_BP_MC_V1 0xA0 286 287 #define HFB_CTRL 0x00 288 #define HFB_FLT_ENABLE_V3PLUS 0x04 289 #define HFB_FLT_LEN_V2 0x04 290 #define HFB_FLT_LEN_V3PLUS 0x1C 291 292 /* uniMac intrl2 registers */ 293 #define INTRL2_CPU_STAT 0x00 294 #define INTRL2_CPU_SET 0x04 295 #define INTRL2_CPU_CLEAR 0x08 296 #define INTRL2_CPU_MASK_STATUS 0x0C 297 #define INTRL2_CPU_MASK_SET 0x10 298 #define INTRL2_CPU_MASK_CLEAR 0x14 299 300 /* INTRL2 instance 0 definitions */ 301 #define UMAC_IRQ_SCB (1 << 0) 302 #define UMAC_IRQ_EPHY (1 << 1) 303 #define UMAC_IRQ_PHY_DET_R (1 << 2) 304 #define UMAC_IRQ_PHY_DET_F (1 << 3) 305 #define UMAC_IRQ_LINK_UP (1 << 4) 306 #define UMAC_IRQ_LINK_DOWN (1 << 5) 307 #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN) 308 #define UMAC_IRQ_UMAC (1 << 6) 309 #define UMAC_IRQ_UMAC_TSV (1 << 7) 310 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 311 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 312 #define UMAC_IRQ_HFB_SM (1 << 10) 313 #define UMAC_IRQ_HFB_MM (1 << 11) 314 #define UMAC_IRQ_MPD_R (1 << 12) 315 #define UMAC_IRQ_WAKE_EVENT (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM | \ 316 UMAC_IRQ_MPD_R) 317 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 318 #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 319 #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 320 #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE 321 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 322 #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 323 #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 324 #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE 325 326 /* Only valid for GENETv3+ */ 327 #define UMAC_IRQ_MDIO_DONE (1 << 23) 328 #define UMAC_IRQ_MDIO_ERROR (1 << 24) 329 330 /* INTRL2 instance 1 definitions */ 331 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF 332 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF 333 #define UMAC_IRQ1_RX_INTR_SHIFT 16 334 335 /* Register block offsets */ 336 #define GENET_SYS_OFF 0x0000 337 #define GENET_GR_BRIDGE_OFF 0x0040 338 #define GENET_EXT_OFF 0x0080 339 #define GENET_INTRL2_0_OFF 0x0200 340 #define GENET_INTRL2_1_OFF 0x0240 341 #define GENET_RBUF_OFF 0x0300 342 #define GENET_UMAC_OFF 0x0800 343 344 /* SYS block offsets and register definitions */ 345 #define SYS_REV_CTRL 0x00 346 #define SYS_PORT_CTRL 0x04 347 #define PORT_MODE_INT_EPHY 0 348 #define PORT_MODE_INT_GPHY 1 349 #define PORT_MODE_EXT_EPHY 2 350 #define PORT_MODE_EXT_GPHY 3 351 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 352 #define PORT_MODE_EXT_RVMII_50 4 353 #define LED_ACT_SOURCE_MAC (1 << 9) 354 355 #define SYS_RBUF_FLUSH_CTRL 0x08 356 #define SYS_TBUF_FLUSH_CTRL 0x0C 357 #define RBUF_FLUSH_CTRL_V1 0x04 358 359 /* Ext block register offsets and definitions */ 360 #define EXT_EXT_PWR_MGMT 0x00 361 #define EXT_PWR_DOWN_BIAS (1 << 0) 362 #define EXT_PWR_DOWN_DLL (1 << 1) 363 #define EXT_PWR_DOWN_PHY (1 << 2) 364 #define EXT_PWR_DN_EN_LD (1 << 3) 365 #define EXT_ENERGY_DET (1 << 4) 366 #define EXT_IDDQ_FROM_PHY (1 << 5) 367 #define EXT_IDDQ_GLBL_PWR (1 << 7) 368 #define EXT_PHY_RESET (1 << 8) 369 #define EXT_ENERGY_DET_MASK (1 << 12) 370 #define EXT_PWR_DOWN_PHY_TX (1 << 16) 371 #define EXT_PWR_DOWN_PHY_RX (1 << 17) 372 #define EXT_PWR_DOWN_PHY_SD (1 << 18) 373 #define EXT_PWR_DOWN_PHY_RD (1 << 19) 374 #define EXT_PWR_DOWN_PHY_EN (1 << 20) 375 376 #define EXT_RGMII_OOB_CTRL 0x0C 377 #define RGMII_MODE_EN_V123 (1 << 0) 378 #define RGMII_LINK (1 << 4) 379 #define OOB_DISABLE (1 << 5) 380 #define RGMII_MODE_EN (1 << 6) 381 #define ID_MODE_DIS (1 << 16) 382 383 #define EXT_GPHY_CTRL 0x1C 384 #define EXT_CFG_IDDQ_BIAS (1 << 0) 385 #define EXT_CFG_PWR_DOWN (1 << 1) 386 #define EXT_CK25_DIS (1 << 4) 387 #define EXT_GPHY_RESET (1 << 5) 388 389 /* DMA rings size */ 390 #define DMA_RING_SIZE (0x40) 391 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 392 393 /* DMA registers common definitions */ 394 #define DMA_RW_POINTER_MASK 0x1FF 395 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 396 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 397 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 398 #define DMA_BUFFER_DONE_CNT_SHIFT 16 399 #define DMA_P_INDEX_MASK 0xFFFF 400 #define DMA_C_INDEX_MASK 0xFFFF 401 402 /* DMA ring size register */ 403 #define DMA_RING_SIZE_MASK 0xFFFF 404 #define DMA_RING_SIZE_SHIFT 16 405 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 406 407 /* DMA interrupt threshold register */ 408 #define DMA_INTR_THRESHOLD_MASK 0x01FF 409 410 /* DMA XON/XOFF register */ 411 #define DMA_XON_THREHOLD_MASK 0xFFFF 412 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 413 #define DMA_XOFF_THRESHOLD_SHIFT 16 414 415 /* DMA flow period register */ 416 #define DMA_FLOW_PERIOD_MASK 0xFFFF 417 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 418 #define DMA_MAX_PKT_SIZE_SHIFT 16 419 420 421 /* DMA control register */ 422 #define DMA_EN (1 << 0) 423 #define DMA_RING_BUF_EN_SHIFT 0x01 424 #define DMA_RING_BUF_EN_MASK 0xFFFF 425 #define DMA_TSB_SWAP_EN (1 << 20) 426 427 /* DMA status register */ 428 #define DMA_DISABLED (1 << 0) 429 #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 430 431 /* DMA SCB burst size register */ 432 #define DMA_SCB_BURST_SIZE_MASK 0x1F 433 434 /* DMA activity vector register */ 435 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 436 437 /* DMA backpressure mask register */ 438 #define DMA_BACKPRESSURE_MASK 0x1FFFF 439 #define DMA_PFC_ENABLE (1 << 31) 440 441 /* DMA backpressure status register */ 442 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 443 444 /* DMA override register */ 445 #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 446 #define DMA_REGISTER_MODE (1 << 1) 447 448 /* DMA timeout register */ 449 #define DMA_TIMEOUT_MASK 0xFFFF 450 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 451 452 /* TDMA rate limiting control register */ 453 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 454 455 /* TDMA arbitration control register */ 456 #define DMA_ARBITER_MODE_MASK 0x03 457 #define DMA_RING_BUF_PRIORITY_MASK 0x1F 458 #define DMA_RING_BUF_PRIORITY_SHIFT 5 459 #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 460 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 461 #define DMA_RATE_ADJ_MASK 0xFF 462 463 /* Tx/Rx Dma Descriptor common bits*/ 464 #define DMA_BUFLENGTH_MASK 0x0fff 465 #define DMA_BUFLENGTH_SHIFT 16 466 #define DMA_OWN 0x8000 467 #define DMA_EOP 0x4000 468 #define DMA_SOP 0x2000 469 #define DMA_WRAP 0x1000 470 /* Tx specific Dma descriptor bits */ 471 #define DMA_TX_UNDERRUN 0x0200 472 #define DMA_TX_APPEND_CRC 0x0040 473 #define DMA_TX_OW_CRC 0x0020 474 #define DMA_TX_DO_CSUM 0x0010 475 #define DMA_TX_QTAG_SHIFT 7 476 477 /* Rx Specific Dma descriptor bits */ 478 #define DMA_RX_CHK_V3PLUS 0x8000 479 #define DMA_RX_CHK_V12 0x1000 480 #define DMA_RX_BRDCAST 0x0040 481 #define DMA_RX_MULT 0x0020 482 #define DMA_RX_LG 0x0010 483 #define DMA_RX_NO 0x0008 484 #define DMA_RX_RXER 0x0004 485 #define DMA_RX_CRC_ERROR 0x0002 486 #define DMA_RX_OV 0x0001 487 #define DMA_RX_FI_MASK 0x001F 488 #define DMA_RX_FI_SHIFT 0x0007 489 #define DMA_DESC_ALLOC_MASK 0x00FF 490 491 #define DMA_ARBITER_RR 0x00 492 #define DMA_ARBITER_WRR 0x01 493 #define DMA_ARBITER_SP 0x02 494 495 struct enet_cb { 496 struct sk_buff *skb; 497 void __iomem *bd_addr; 498 DEFINE_DMA_UNMAP_ADDR(dma_addr); 499 DEFINE_DMA_UNMAP_LEN(dma_len); 500 }; 501 502 /* power management mode */ 503 enum bcmgenet_power_mode { 504 GENET_POWER_CABLE_SENSE = 0, 505 GENET_POWER_PASSIVE, 506 GENET_POWER_WOL_MAGIC, 507 }; 508 509 struct bcmgenet_priv; 510 511 /* We support both runtime GENET detection and compile-time 512 * to optimize code-paths for a given hardware 513 */ 514 enum bcmgenet_version { 515 GENET_V1 = 1, 516 GENET_V2, 517 GENET_V3, 518 GENET_V4, 519 GENET_V5 520 }; 521 522 #define GENET_IS_V1(p) ((p)->version == GENET_V1) 523 #define GENET_IS_V2(p) ((p)->version == GENET_V2) 524 #define GENET_IS_V3(p) ((p)->version == GENET_V3) 525 #define GENET_IS_V4(p) ((p)->version == GENET_V4) 526 #define GENET_IS_V5(p) ((p)->version == GENET_V5) 527 528 /* Hardware flags */ 529 #define GENET_HAS_40BITS (1 << 0) 530 #define GENET_HAS_EXT (1 << 1) 531 #define GENET_HAS_MDIO_INTR (1 << 2) 532 #define GENET_HAS_MOCA_LINK_DET (1 << 3) 533 534 /* BCMGENET hardware parameters, keep this structure nicely aligned 535 * since it is going to be used in hot paths 536 */ 537 struct bcmgenet_hw_params { 538 u8 tx_queues; 539 u8 tx_bds_per_q; 540 u8 rx_queues; 541 u8 rx_bds_per_q; 542 u8 bp_in_en_shift; 543 u32 bp_in_mask; 544 u8 hfb_filter_cnt; 545 u8 hfb_filter_size; 546 u8 qtag_mask; 547 u16 tbuf_offset; 548 u32 hfb_offset; 549 u32 hfb_reg_offset; 550 u32 rdma_offset; 551 u32 tdma_offset; 552 u32 words_per_bd; 553 u32 flags; 554 }; 555 556 struct bcmgenet_skb_cb { 557 struct enet_cb *first_cb; /* First control block of SKB */ 558 struct enet_cb *last_cb; /* Last control block of SKB */ 559 unsigned int bytes_sent; /* bytes on the wire (no TSB) */ 560 }; 561 562 #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb)) 563 564 struct bcmgenet_tx_ring { 565 spinlock_t lock; /* ring lock */ 566 struct napi_struct napi; /* NAPI per tx queue */ 567 unsigned long packets; 568 unsigned long bytes; 569 unsigned int index; /* ring index */ 570 unsigned int queue; /* queue index */ 571 struct enet_cb *cbs; /* tx ring buffer control block*/ 572 unsigned int size; /* size of each tx ring */ 573 unsigned int clean_ptr; /* Tx ring clean pointer */ 574 unsigned int c_index; /* last consumer index of each ring*/ 575 unsigned int free_bds; /* # of free bds for each ring */ 576 unsigned int write_ptr; /* Tx ring write pointer SW copy */ 577 unsigned int prod_index; /* Tx ring producer index SW copy */ 578 unsigned int cb_ptr; /* Tx ring initial CB ptr */ 579 unsigned int end_ptr; /* Tx ring end CB ptr */ 580 void (*int_enable)(struct bcmgenet_tx_ring *); 581 void (*int_disable)(struct bcmgenet_tx_ring *); 582 struct bcmgenet_priv *priv; 583 }; 584 585 struct bcmgenet_net_dim { 586 u16 use_dim; 587 u16 event_ctr; 588 unsigned long packets; 589 unsigned long bytes; 590 struct dim dim; 591 }; 592 593 struct bcmgenet_rx_ring { 594 struct napi_struct napi; /* Rx NAPI struct */ 595 unsigned long bytes; 596 unsigned long packets; 597 unsigned long errors; 598 unsigned long dropped; 599 unsigned int index; /* Rx ring index */ 600 struct enet_cb *cbs; /* Rx ring buffer control block */ 601 unsigned int size; /* Rx ring size */ 602 unsigned int c_index; /* Rx last consumer index */ 603 unsigned int read_ptr; /* Rx ring read pointer */ 604 unsigned int cb_ptr; /* Rx ring initial CB ptr */ 605 unsigned int end_ptr; /* Rx ring end CB ptr */ 606 unsigned int old_discards; 607 struct bcmgenet_net_dim dim; 608 u32 rx_max_coalesced_frames; 609 u32 rx_coalesce_usecs; 610 void (*int_enable)(struct bcmgenet_rx_ring *); 611 void (*int_disable)(struct bcmgenet_rx_ring *); 612 struct bcmgenet_priv *priv; 613 }; 614 615 enum bcmgenet_rxnfc_state { 616 BCMGENET_RXNFC_STATE_UNUSED = 0, 617 BCMGENET_RXNFC_STATE_DISABLED, 618 BCMGENET_RXNFC_STATE_ENABLED 619 }; 620 621 struct bcmgenet_rxnfc_rule { 622 struct list_head list; 623 struct ethtool_rx_flow_spec fs; 624 enum bcmgenet_rxnfc_state state; 625 }; 626 627 /* device context */ 628 struct bcmgenet_priv { 629 void __iomem *base; 630 enum bcmgenet_version version; 631 struct net_device *dev; 632 633 /* transmit variables */ 634 void __iomem *tx_bds; 635 struct enet_cb *tx_cbs; 636 unsigned int num_tx_bds; 637 638 struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; 639 640 /* receive variables */ 641 void __iomem *rx_bds; 642 struct enet_cb *rx_cbs; 643 unsigned int num_rx_bds; 644 unsigned int rx_buf_len; 645 struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES]; 646 struct list_head rxnfc_list; 647 648 struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1]; 649 650 /* other misc variables */ 651 struct bcmgenet_hw_params *hw_params; 652 653 /* MDIO bus variables */ 654 wait_queue_head_t wq; 655 bool internal_phy; 656 struct device_node *phy_dn; 657 struct device_node *mdio_dn; 658 struct mii_bus *mii_bus; 659 u16 gphy_rev; 660 struct clk *clk_eee; 661 bool clk_eee_enabled; 662 663 /* PHY device variables */ 664 int old_link; 665 int old_speed; 666 int old_duplex; 667 int old_pause; 668 phy_interface_t phy_interface; 669 int phy_addr; 670 int ext_phy; 671 672 /* Interrupt variables */ 673 struct work_struct bcmgenet_irq_work; 674 int irq0; 675 int irq1; 676 int wol_irq; 677 bool wol_irq_disabled; 678 679 /* shared status */ 680 spinlock_t lock; 681 unsigned int irq0_stat; 682 683 /* HW descriptors/checksum variables */ 684 bool crc_fwd_en; 685 686 u32 dma_max_burst_length; 687 688 u32 msg_enable; 689 690 struct clk *clk; 691 struct platform_device *pdev; 692 struct platform_device *mii_pdev; 693 694 /* WOL */ 695 struct clk *clk_wol; 696 u32 wolopts; 697 u8 sopass[SOPASS_MAX]; 698 bool wol_active; 699 700 struct bcmgenet_mib_counters mib; 701 702 struct ethtool_eee eee; 703 }; 704 705 #define GENET_IO_MACRO(name, offset) \ 706 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 707 u32 off) \ 708 { \ 709 /* MIPS chips strapped for BE will automagically configure the \ 710 * peripheral registers for CPU-native byte order. \ 711 */ \ 712 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 713 return __raw_readl(priv->base + offset + off); \ 714 else \ 715 return readl_relaxed(priv->base + offset + off); \ 716 } \ 717 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 718 u32 val, u32 off) \ 719 { \ 720 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 721 __raw_writel(val, priv->base + offset + off); \ 722 else \ 723 writel_relaxed(val, priv->base + offset + off); \ 724 } 725 726 GENET_IO_MACRO(ext, GENET_EXT_OFF); 727 GENET_IO_MACRO(umac, GENET_UMAC_OFF); 728 GENET_IO_MACRO(sys, GENET_SYS_OFF); 729 730 /* interrupt l2 registers accessors */ 731 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 732 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 733 734 /* HFB register accessors */ 735 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 736 737 /* GENET v2+ HFB control and filter len helpers */ 738 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 739 740 /* RBUF register accessors */ 741 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 742 743 /* MDIO routines */ 744 int bcmgenet_mii_init(struct net_device *dev); 745 int bcmgenet_mii_config(struct net_device *dev, bool init); 746 int bcmgenet_mii_probe(struct net_device *dev); 747 void bcmgenet_mii_exit(struct net_device *dev); 748 void bcmgenet_phy_power_set(struct net_device *dev, bool enable); 749 void bcmgenet_mii_setup(struct net_device *dev); 750 751 /* Wake-on-LAN routines */ 752 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 753 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 754 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 755 enum bcmgenet_power_mode mode); 756 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 757 enum bcmgenet_power_mode mode); 758 759 #endif /* __BCMGENET_H__ */ 760
