1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HW_TYPES_H 27 #define DC_HW_TYPES_H 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "signal_types.h" 32 33 /****************************************************************************** 34 * Data types for Virtual HW Layer of DAL3. 35 * (see DAL3 design documents for HW Layer definition) 36 * 37 * The intended uses are: 38 * 1. Generation pseudocode sequences for HW programming. 39 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 40 * 41 * Note: do *not* add any types which are *not* used for HW programming - this 42 * will ensure separation of Logic layer from HW layer. 43 ******************************************************************************/ 44 45 union large_integer { 46 struct { 47 uint32_t low_part; 48 int32_t high_part; 49 }; 50 51 struct { 52 uint32_t low_part; 53 int32_t high_part; 54 } u; 55 56 int64_t quad_part; 57 }; 58 59 #define PHYSICAL_ADDRESS_LOC union large_integer 60 61 enum dc_plane_addr_type { 62 PLN_ADDR_TYPE_GRAPHICS = 0, 63 PLN_ADDR_TYPE_GRPH_STEREO, 64 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 65 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 66 PLN_ADDR_TYPE_RGBEA 67 #endif 68 }; 69 70 struct dc_plane_address { 71 enum dc_plane_addr_type type; 72 bool tmz_surface; 73 union { 74 struct{ 75 PHYSICAL_ADDRESS_LOC addr; 76 PHYSICAL_ADDRESS_LOC meta_addr; 77 union large_integer dcc_const_color; 78 } grph; 79 80 /*stereo*/ 81 struct { 82 PHYSICAL_ADDRESS_LOC left_addr; 83 PHYSICAL_ADDRESS_LOC left_meta_addr; 84 union large_integer left_dcc_const_color; 85 86 PHYSICAL_ADDRESS_LOC right_addr; 87 PHYSICAL_ADDRESS_LOC right_meta_addr; 88 union large_integer right_dcc_const_color; 89 90 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 91 PHYSICAL_ADDRESS_LOC left_alpha_addr; 92 PHYSICAL_ADDRESS_LOC left_alpha_meta_addr; 93 union large_integer left_alpha_dcc_const_color; 94 95 PHYSICAL_ADDRESS_LOC right_alpha_addr; 96 PHYSICAL_ADDRESS_LOC right_alpha_meta_addr; 97 union large_integer right_alpha_dcc_const_color; 98 #endif 99 100 } grph_stereo; 101 102 /*video progressive*/ 103 struct { 104 PHYSICAL_ADDRESS_LOC luma_addr; 105 PHYSICAL_ADDRESS_LOC luma_meta_addr; 106 union large_integer luma_dcc_const_color; 107 108 PHYSICAL_ADDRESS_LOC chroma_addr; 109 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 110 union large_integer chroma_dcc_const_color; 111 } video_progressive; 112 113 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 114 struct { 115 PHYSICAL_ADDRESS_LOC addr; 116 PHYSICAL_ADDRESS_LOC meta_addr; 117 union large_integer dcc_const_color; 118 119 PHYSICAL_ADDRESS_LOC alpha_addr; 120 PHYSICAL_ADDRESS_LOC alpha_meta_addr; 121 union large_integer alpha_dcc_const_color; 122 } rgbea; 123 #endif 124 }; 125 126 union large_integer page_table_base; 127 128 uint8_t vmid; 129 }; 130 131 struct dc_size { 132 int width; 133 int height; 134 }; 135 136 struct rect { 137 int x; 138 int y; 139 int width; 140 int height; 141 }; 142 143 struct plane_size { 144 /* Graphic surface pitch in pixels. 145 * In LINEAR_GENERAL mode, pitch 146 * is 32 pixel aligned. 147 */ 148 int surface_pitch; 149 int chroma_pitch; 150 struct rect surface_size; 151 struct rect chroma_size; 152 }; 153 154 struct dc_plane_dcc_param { 155 bool enable; 156 157 int meta_pitch; 158 bool independent_64b_blks; 159 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 160 uint8_t dcc_ind_blk; 161 #endif 162 163 int meta_pitch_c; 164 bool independent_64b_blks_c; 165 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 166 uint8_t dcc_ind_blk_c; 167 #endif 168 }; 169 170 /*Displayable pixel format in fb*/ 171 enum surface_pixel_format { 172 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 173 /*TOBE REMOVED paletta 256 colors*/ 174 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 175 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 176 /*16 bpp*/ 177 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 178 /*16 bpp*/ 179 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 180 /*32 bpp*/ 181 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 182 /*32 bpp swaped*/ 183 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 184 185 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 186 /*swaped*/ 187 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 188 /*TOBE REMOVED swaped, XR_BIAS has no differance 189 * for pixel layout than previous and we can 190 * delete this after discusion*/ 191 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 192 /*64 bpp */ 193 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 194 /*float*/ 195 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 196 /*swaped & float*/ 197 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 198 /*grow graphics here if necessary */ 199 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 200 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 201 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 202 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 203 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 204 SURFACE_PIXEL_FORMAT_GRPH_RGBE, 205 SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 206 #endif 207 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 208 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 209 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 210 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 211 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 212 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 213 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 214 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, 215 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 216 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 217 SURFACE_PIXEL_FORMAT_INVALID 218 219 /*grow 444 video here if necessary */ 220 }; 221 222 223 224 /* Pixel format */ 225 enum pixel_format { 226 /*graph*/ 227 PIXEL_FORMAT_UNINITIALIZED, 228 PIXEL_FORMAT_INDEX8, 229 PIXEL_FORMAT_RGB565, 230 PIXEL_FORMAT_ARGB8888, 231 PIXEL_FORMAT_ARGB2101010, 232 PIXEL_FORMAT_ARGB2101010_XRBIAS, 233 PIXEL_FORMAT_FP16, 234 /*video*/ 235 PIXEL_FORMAT_420BPP8, 236 PIXEL_FORMAT_420BPP10, 237 /*end of pixel format definition*/ 238 PIXEL_FORMAT_INVALID, 239 240 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 241 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 242 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 243 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 244 PIXEL_FORMAT_UNKNOWN 245 }; 246 247 enum tile_split_values { 248 DC_DISPLAY_MICRO_TILING = 0x0, 249 DC_THIN_MICRO_TILING = 0x1, 250 DC_DEPTH_MICRO_TILING = 0x2, 251 DC_ROTATED_MICRO_TILING = 0x3, 252 }; 253 254 enum tripleBuffer_enable { 255 DC_TRIPLEBUFFER_DISABLE = 0x0, 256 DC_TRIPLEBUFFER_ENABLE = 0x1, 257 }; 258 259 /* TODO: These values come from hardware spec. We need to readdress this 260 * if they ever change. 261 */ 262 enum array_mode_values { 263 DC_ARRAY_LINEAR_GENERAL = 0, 264 DC_ARRAY_LINEAR_ALLIGNED, 265 DC_ARRAY_1D_TILED_THIN1, 266 DC_ARRAY_1D_TILED_THICK, 267 DC_ARRAY_2D_TILED_THIN1, 268 DC_ARRAY_PRT_TILED_THIN1, 269 DC_ARRAY_PRT_2D_TILED_THIN1, 270 DC_ARRAY_2D_TILED_THICK, 271 DC_ARRAY_2D_TILED_X_THICK, 272 DC_ARRAY_PRT_TILED_THICK, 273 DC_ARRAY_PRT_2D_TILED_THICK, 274 DC_ARRAY_PRT_3D_TILED_THIN1, 275 DC_ARRAY_3D_TILED_THIN1, 276 DC_ARRAY_3D_TILED_THICK, 277 DC_ARRAY_3D_TILED_X_THICK, 278 DC_ARRAY_PRT_3D_TILED_THICK, 279 }; 280 281 enum tile_mode_values { 282 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 283 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 284 }; 285 286 enum swizzle_mode_values { 287 DC_SW_LINEAR = 0, 288 DC_SW_256B_S = 1, 289 DC_SW_256_D = 2, 290 DC_SW_256_R = 3, 291 DC_SW_4KB_S = 5, 292 DC_SW_4KB_D = 6, 293 DC_SW_4KB_R = 7, 294 DC_SW_64KB_S = 9, 295 DC_SW_64KB_D = 10, 296 DC_SW_64KB_R = 11, 297 DC_SW_VAR_S = 13, 298 DC_SW_VAR_D = 14, 299 DC_SW_VAR_R = 15, 300 DC_SW_64KB_S_T = 17, 301 DC_SW_64KB_D_T = 18, 302 DC_SW_4KB_S_X = 21, 303 DC_SW_4KB_D_X = 22, 304 DC_SW_4KB_R_X = 23, 305 DC_SW_64KB_S_X = 25, 306 DC_SW_64KB_D_X = 26, 307 DC_SW_64KB_R_X = 27, 308 DC_SW_VAR_S_X = 29, 309 DC_SW_VAR_D_X = 30, 310 DC_SW_VAR_R_X = 31, 311 DC_SW_MAX = 32, 312 DC_SW_UNKNOWN = DC_SW_MAX 313 }; 314 315 union dc_tiling_info { 316 317 struct { 318 /* Specifies the number of memory banks for tiling 319 * purposes. 320 * Only applies to 2D and 3D tiling modes. 321 * POSSIBLE VALUES: 2,4,8,16 322 */ 323 unsigned int num_banks; 324 /* Specifies the number of tiles in the x direction 325 * to be incorporated into the same bank. 326 * Only applies to 2D and 3D tiling modes. 327 * POSSIBLE VALUES: 1,2,4,8 328 */ 329 unsigned int bank_width; 330 unsigned int bank_width_c; 331 /* Specifies the number of tiles in the y direction to 332 * be incorporated into the same bank. 333 * Only applies to 2D and 3D tiling modes. 334 * POSSIBLE VALUES: 1,2,4,8 335 */ 336 unsigned int bank_height; 337 unsigned int bank_height_c; 338 /* Specifies the macro tile aspect ratio. Only applies 339 * to 2D and 3D tiling modes. 340 */ 341 unsigned int tile_aspect; 342 unsigned int tile_aspect_c; 343 /* Specifies the number of bytes that will be stored 344 * contiguously for each tile. 345 * If the tile data requires more storage than this 346 * amount, it is split into multiple slices. 347 * This field must not be larger than 348 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 349 * Only applies to 2D and 3D tiling modes. 350 * For color render targets, TILE_SPLIT >= 256B. 351 */ 352 enum tile_split_values tile_split; 353 enum tile_split_values tile_split_c; 354 /* Specifies the addressing within a tile. 355 * 0x0 - DISPLAY_MICRO_TILING 356 * 0x1 - THIN_MICRO_TILING 357 * 0x2 - DEPTH_MICRO_TILING 358 * 0x3 - ROTATED_MICRO_TILING 359 */ 360 enum tile_mode_values tile_mode; 361 enum tile_mode_values tile_mode_c; 362 /* Specifies the number of pipes and how they are 363 * interleaved in the surface. 364 * Refer to memory addressing document for complete 365 * details and constraints. 366 */ 367 unsigned int pipe_config; 368 /* Specifies the tiling mode of the surface. 369 * THIN tiles use an 8x8x1 tile size. 370 * THICK tiles use an 8x8x4 tile size. 371 * 2D tiling modes rotate banks for successive Z slices 372 * 3D tiling modes rotate pipes and banks for Z slices 373 * Refer to memory addressing document for complete 374 * details and constraints. 375 */ 376 enum array_mode_values array_mode; 377 } gfx8; 378 379 struct { 380 enum swizzle_mode_values swizzle; 381 unsigned int num_pipes; 382 unsigned int max_compressed_frags; 383 unsigned int pipe_interleave; 384 385 unsigned int num_banks; 386 unsigned int num_shader_engines; 387 unsigned int num_rb_per_se; 388 bool shaderEnable; 389 390 bool meta_linear; 391 bool rb_aligned; 392 bool pipe_aligned; 393 unsigned int num_pkrs; 394 } gfx9; 395 }; 396 397 /* Rotation angle */ 398 enum dc_rotation_angle { 399 ROTATION_ANGLE_0 = 0, 400 ROTATION_ANGLE_90, 401 ROTATION_ANGLE_180, 402 ROTATION_ANGLE_270, 403 ROTATION_ANGLE_COUNT 404 }; 405 406 enum dc_scan_direction { 407 SCAN_DIRECTION_UNKNOWN = 0, 408 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 409 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 410 }; 411 412 struct dc_cursor_position { 413 uint32_t x; 414 uint32_t y; 415 416 uint32_t x_hotspot; 417 uint32_t y_hotspot; 418 419 /* 420 * This parameter indicates whether HW cursor should be enabled 421 */ 422 bool enable; 423 424 /* Translate cursor x/y by the source rectangle for each plane. */ 425 bool translate_by_source; 426 }; 427 428 struct dc_cursor_mi_param { 429 unsigned int pixel_clk_khz; 430 unsigned int ref_clk_khz; 431 struct rect viewport; 432 struct fixed31_32 h_scale_ratio; 433 struct fixed31_32 v_scale_ratio; 434 enum dc_rotation_angle rotation; 435 bool mirror; 436 }; 437 438 /* IPP related types */ 439 440 enum { 441 GAMMA_RGB_256_ENTRIES = 256, 442 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 443 GAMMA_CS_TFM_1D_ENTRIES = 4096, 444 GAMMA_CUSTOM_ENTRIES = 4096, 445 GAMMA_MAX_ENTRIES = 4096 446 }; 447 448 enum dc_gamma_type { 449 GAMMA_RGB_256 = 1, 450 GAMMA_RGB_FLOAT_1024 = 2, 451 GAMMA_CS_TFM_1D = 3, 452 GAMMA_CUSTOM = 4, 453 }; 454 455 struct dc_csc_transform { 456 uint16_t matrix[12]; 457 bool enable_adjustment; 458 }; 459 460 struct dc_rgb_fixed { 461 struct fixed31_32 red; 462 struct fixed31_32 green; 463 struct fixed31_32 blue; 464 }; 465 466 struct dc_gamma { 467 struct kref refcount; 468 enum dc_gamma_type type; 469 unsigned int num_entries; 470 471 struct dc_gamma_entries { 472 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 473 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 474 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 475 } entries; 476 477 /* private to DC core */ 478 struct dc_context *ctx; 479 480 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 481 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 482 */ 483 bool is_identity; 484 }; 485 486 /* Used by both ipp amd opp functions*/ 487 /* TODO: to be consolidated with enum color_space */ 488 489 /* 490 * This enum is for programming CURSOR_MODE register field. What this register 491 * should be programmed to depends on OS requested cursor shape flags and what 492 * we stored in the cursor surface. 493 */ 494 enum dc_cursor_color_format { 495 CURSOR_MODE_MONO, 496 CURSOR_MODE_COLOR_1BIT_AND, 497 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 498 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 499 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 500 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 501 }; 502 503 /* 504 * This is all the parameters required by DAL in order to update the cursor 505 * attributes, including the new cursor image surface address, size, hotspot 506 * location, color format, etc. 507 */ 508 509 union dc_cursor_attribute_flags { 510 struct { 511 uint32_t ENABLE_MAGNIFICATION:1; 512 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 513 uint32_t HORIZONTAL_MIRROR:1; 514 uint32_t VERTICAL_MIRROR:1; 515 uint32_t INVERT_PIXEL_DATA:1; 516 uint32_t ZERO_EXPANSION:1; 517 uint32_t MIN_MAX_INVERT:1; 518 uint32_t ENABLE_CURSOR_DEGAMMA:1; 519 uint32_t RESERVED:24; 520 } bits; 521 uint32_t value; 522 }; 523 524 struct dc_cursor_attributes { 525 PHYSICAL_ADDRESS_LOC address; 526 uint32_t pitch; 527 528 /* Width and height should correspond to cursor surface width x heigh */ 529 uint32_t width; 530 uint32_t height; 531 532 enum dc_cursor_color_format color_format; 533 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 534 535 /* In case we support HW Cursor rotation in the future */ 536 enum dc_rotation_angle rotation_angle; 537 538 union dc_cursor_attribute_flags attribute_flags; 539 }; 540 541 struct dpp_cursor_attributes { 542 int bias; 543 int scale; 544 }; 545 546 /* OPP */ 547 548 enum dc_color_space { 549 COLOR_SPACE_UNKNOWN, 550 COLOR_SPACE_SRGB, 551 COLOR_SPACE_XR_RGB, 552 COLOR_SPACE_SRGB_LIMITED, 553 COLOR_SPACE_MSREF_SCRGB, 554 COLOR_SPACE_YCBCR601, 555 COLOR_SPACE_YCBCR709, 556 COLOR_SPACE_XV_YCC_709, 557 COLOR_SPACE_XV_YCC_601, 558 COLOR_SPACE_YCBCR601_LIMITED, 559 COLOR_SPACE_YCBCR709_LIMITED, 560 COLOR_SPACE_2020_RGB_FULLRANGE, 561 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 562 COLOR_SPACE_2020_YCBCR, 563 COLOR_SPACE_ADOBERGB, 564 COLOR_SPACE_DCIP3, 565 COLOR_SPACE_DISPLAYNATIVE, 566 COLOR_SPACE_DOLBYVISION, 567 COLOR_SPACE_APPCTRL, 568 COLOR_SPACE_CUSTOMPOINTS, 569 COLOR_SPACE_YCBCR709_BLACK, 570 }; 571 572 enum dc_dither_option { 573 DITHER_OPTION_DEFAULT, 574 DITHER_OPTION_DISABLE, 575 DITHER_OPTION_FM6, 576 DITHER_OPTION_FM8, 577 DITHER_OPTION_FM10, 578 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 579 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 580 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 581 DITHER_OPTION_SPATIAL6, 582 DITHER_OPTION_SPATIAL8, 583 DITHER_OPTION_SPATIAL10, 584 DITHER_OPTION_TRUN6, 585 DITHER_OPTION_TRUN8, 586 DITHER_OPTION_TRUN10, 587 DITHER_OPTION_TRUN10_SPATIAL8, 588 DITHER_OPTION_TRUN10_SPATIAL6, 589 DITHER_OPTION_TRUN10_FM8, 590 DITHER_OPTION_TRUN10_FM6, 591 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 592 DITHER_OPTION_SPATIAL10_FM8, 593 DITHER_OPTION_SPATIAL10_FM6, 594 DITHER_OPTION_TRUN8_SPATIAL6, 595 DITHER_OPTION_TRUN8_FM6, 596 DITHER_OPTION_SPATIAL8_FM6, 597 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 598 DITHER_OPTION_INVALID 599 }; 600 601 enum dc_quantization_range { 602 QUANTIZATION_RANGE_UNKNOWN, 603 QUANTIZATION_RANGE_FULL, 604 QUANTIZATION_RANGE_LIMITED 605 }; 606 607 enum dc_dynamic_expansion { 608 DYN_EXPANSION_AUTO, 609 DYN_EXPANSION_DISABLE 610 }; 611 612 /* XFM */ 613 614 /* used in struct dc_plane_state */ 615 struct scaling_taps { 616 uint32_t v_taps; 617 uint32_t h_taps; 618 uint32_t v_taps_c; 619 uint32_t h_taps_c; 620 bool integer_scaling; 621 }; 622 623 enum dc_timing_standard { 624 DC_TIMING_STANDARD_UNDEFINED, 625 DC_TIMING_STANDARD_DMT, 626 DC_TIMING_STANDARD_GTF, 627 DC_TIMING_STANDARD_CVT, 628 DC_TIMING_STANDARD_CVT_RB, 629 DC_TIMING_STANDARD_CEA770, 630 DC_TIMING_STANDARD_CEA861, 631 DC_TIMING_STANDARD_HDMI, 632 DC_TIMING_STANDARD_TV_NTSC, 633 DC_TIMING_STANDARD_TV_NTSC_J, 634 DC_TIMING_STANDARD_TV_PAL, 635 DC_TIMING_STANDARD_TV_PAL_M, 636 DC_TIMING_STANDARD_TV_PAL_CN, 637 DC_TIMING_STANDARD_TV_SECAM, 638 DC_TIMING_STANDARD_EXPLICIT, 639 /*!< For explicit timings from EDID, VBIOS, etc.*/ 640 DC_TIMING_STANDARD_USER_OVERRIDE, 641 /*!< For mode timing override by user*/ 642 DC_TIMING_STANDARD_MAX 643 }; 644 645 enum dc_color_depth { 646 COLOR_DEPTH_UNDEFINED, 647 COLOR_DEPTH_666, 648 COLOR_DEPTH_888, 649 COLOR_DEPTH_101010, 650 COLOR_DEPTH_121212, 651 COLOR_DEPTH_141414, 652 COLOR_DEPTH_161616, 653 COLOR_DEPTH_999, 654 COLOR_DEPTH_111111, 655 COLOR_DEPTH_COUNT 656 }; 657 658 enum dc_pixel_encoding { 659 PIXEL_ENCODING_UNDEFINED, 660 PIXEL_ENCODING_RGB, 661 PIXEL_ENCODING_YCBCR422, 662 PIXEL_ENCODING_YCBCR444, 663 PIXEL_ENCODING_YCBCR420, 664 PIXEL_ENCODING_COUNT 665 }; 666 667 enum dc_aspect_ratio { 668 ASPECT_RATIO_NO_DATA, 669 ASPECT_RATIO_4_3, 670 ASPECT_RATIO_16_9, 671 ASPECT_RATIO_64_27, 672 ASPECT_RATIO_256_135, 673 ASPECT_RATIO_FUTURE 674 }; 675 676 enum scanning_type { 677 SCANNING_TYPE_NODATA = 0, 678 SCANNING_TYPE_OVERSCAN, 679 SCANNING_TYPE_UNDERSCAN, 680 SCANNING_TYPE_FUTURE, 681 SCANNING_TYPE_UNDEFINED 682 }; 683 684 struct dc_crtc_timing_flags { 685 uint32_t INTERLACE :1; 686 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 687 it is positive polarity --reversed with dal1 or video bios define*/ 688 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 689 it is positive polarity --reversed with dal1 or video bios define*/ 690 691 uint32_t HORZ_COUNT_BY_TWO:1; 692 693 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 694 timing can be driven in 3D format only 695 and there is no corresponding 2D timing*/ 696 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 697 (right eye = '1', left eye = '0') */ 698 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 699 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 700 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 701 because corresponding 2D timing also present in the list*/ 702 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 703 and we want to match priority of corresponding 3D timing*/ 704 uint32_t Y_ONLY :1; 705 706 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 707 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 708 709 uint32_t FORCE_HDR :1; 710 711 /* HDMI 2.0 - Support scrambling for TMDS character 712 * rates less than or equal to 340Mcsc */ 713 uint32_t LTE_340MCSC_SCRAMBLE:1; 714 715 uint32_t DSC : 1; /* Use DSC with this timing */ 716 #ifndef TRIM_FSFT 717 uint32_t FAST_TRANSPORT: 1; 718 #endif 719 }; 720 721 enum dc_timing_3d_format { 722 TIMING_3D_FORMAT_NONE, 723 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 724 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 725 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 726 /* for active DP-HDMI dongle*/ 727 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 728 TIMING_3D_FORMAT_HW_FRAME_PACKING, 729 TIMING_3D_FORMAT_SW_FRAME_PACKING, 730 TIMING_3D_FORMAT_ROW_INTERLEAVE, 731 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 732 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 733 TIMING_3D_FORMAT_SIDE_BY_SIDE, 734 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 735 TIMING_3D_FORMAT_SBS_SW_PACKED, 736 /* Side-by-side, packed by application/driver into 2D frame*/ 737 TIMING_3D_FORMAT_TB_SW_PACKED, 738 /* Top-and-bottom, packed by application/driver into 2D frame*/ 739 740 TIMING_3D_FORMAT_MAX, 741 }; 742 743 struct dc_dsc_config { 744 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 745 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 746 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 747 bool block_pred_enable; /* DSC block prediction enable */ 748 uint32_t linebuf_depth; /* DSC line buffer depth */ 749 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 750 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 751 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 752 }; 753 struct dc_crtc_timing { 754 uint32_t h_total; 755 uint32_t h_border_left; 756 uint32_t h_addressable; 757 uint32_t h_border_right; 758 uint32_t h_front_porch; 759 uint32_t h_sync_width; 760 761 uint32_t v_total; 762 uint32_t v_border_top; 763 uint32_t v_addressable; 764 uint32_t v_border_bottom; 765 uint32_t v_front_porch; 766 uint32_t v_sync_width; 767 768 uint32_t pix_clk_100hz; 769 770 uint32_t vic; 771 uint32_t hdmi_vic; 772 enum dc_timing_3d_format timing_3d_format; 773 enum dc_color_depth display_color_depth; 774 enum dc_pixel_encoding pixel_encoding; 775 enum dc_aspect_ratio aspect_ratio; 776 enum scanning_type scan_type; 777 778 #ifndef TRIM_FSFT 779 uint32_t fast_transport_output_rate_100hz; 780 #endif 781 782 struct dc_crtc_timing_flags flags; 783 struct dc_dsc_config dsc_cfg; 784 }; 785 786 enum trigger_delay { 787 TRIGGER_DELAY_NEXT_PIXEL = 0, 788 TRIGGER_DELAY_NEXT_LINE, 789 }; 790 791 enum crtc_event { 792 CRTC_EVENT_VSYNC_RISING = 0, 793 CRTC_EVENT_VSYNC_FALLING 794 }; 795 796 struct crtc_trigger_info { 797 bool enabled; 798 struct dc_stream_state *event_source; 799 enum crtc_event event; 800 enum trigger_delay delay; 801 }; 802 803 struct dc_crtc_timing_adjust { 804 uint32_t v_total_min; 805 uint32_t v_total_max; 806 uint32_t v_total_mid; 807 uint32_t v_total_mid_frame_num; 808 }; 809 810 811 /* Passed on init */ 812 enum vram_type { 813 VIDEO_MEMORY_TYPE_GDDR5 = 2, 814 VIDEO_MEMORY_TYPE_DDR3 = 3, 815 VIDEO_MEMORY_TYPE_DDR4 = 4, 816 VIDEO_MEMORY_TYPE_HBM = 5, 817 VIDEO_MEMORY_TYPE_GDDR6 = 6, 818 }; 819 820 enum dwb_cnv_out_bpc { 821 DWB_CNV_OUT_BPC_8BPC = 0, 822 DWB_CNV_OUT_BPC_10BPC = 1, 823 }; 824 825 enum dwb_output_depth { 826 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 827 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 828 }; 829 830 enum dwb_capture_rate { 831 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 832 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 833 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 834 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 835 }; 836 837 enum dwb_scaler_mode { 838 dwb_scaler_mode_bypass444 = 0, 839 dwb_scaler_mode_rgb444 = 1, 840 dwb_scaler_mode_yuv444 = 2, 841 dwb_scaler_mode_yuv420 = 3 842 }; 843 844 enum dwb_subsample_position { 845 DWB_INTERSTITIAL_SUBSAMPLING = 0, 846 DWB_COSITED_SUBSAMPLING = 1 847 }; 848 849 enum dwb_stereo_eye_select { 850 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 851 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 852 }; 853 854 enum dwb_stereo_type { 855 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 856 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 857 }; 858 859 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 860 861 enum dwb_out_format { 862 DWB_OUT_FORMAT_32BPP_ARGB = 0, 863 DWB_OUT_FORMAT_32BPP_RGBA = 1, 864 DWB_OUT_FORMAT_64BPP_ARGB = 2, 865 DWB_OUT_FORMAT_64BPP_RGBA = 3 866 }; 867 868 enum dwb_out_denorm { 869 DWB_OUT_DENORM_10BPC = 0, 870 DWB_OUT_DENORM_8BPC = 1, 871 DWB_OUT_DENORM_BYPASS = 2 872 }; 873 874 enum cm_gamut_remap_select { 875 CM_GAMUT_REMAP_MODE_BYPASS = 0, 876 CM_GAMUT_REMAP_MODE_RAMA_COEFF, 877 CM_GAMUT_REMAP_MODE_RAMB_COEFF, 878 CM_GAMUT_REMAP_MODE_RESERVED 879 }; 880 881 enum cm_gamut_coef_format { 882 CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0, 883 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 884 }; 885 886 struct mcif_warmup_params { 887 union large_integer start_address; 888 unsigned int address_increment; 889 unsigned int region_size; 890 unsigned int p_vmid; 891 }; 892 893 #endif 894 895 #define MCIF_BUF_COUNT 4 896 897 struct mcif_buf_params { 898 unsigned long long luma_address[MCIF_BUF_COUNT]; 899 unsigned long long chroma_address[MCIF_BUF_COUNT]; 900 unsigned int luma_pitch; 901 unsigned int chroma_pitch; 902 unsigned int warmup_pitch; 903 unsigned int swlock; 904 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 905 unsigned int p_vmid; 906 #endif 907 }; 908 909 910 #define MAX_TG_COLOR_VALUE 0x3FF 911 struct tg_color { 912 /* Maximum 10 bits color value */ 913 uint16_t color_r_cr; 914 uint16_t color_g_y; 915 uint16_t color_b_cb; 916 }; 917 918 #endif /* DC_HW_TYPES_H */ 919 920
