Searched refs:Chipset (Results 1 – 19 of 19) sorted by relevance
22 7 Series Chipset Family23 6 Series Chipset Family24 5 Series Chipset Family25 4 Series Chipset Family26 Mobile 4 Series Chipset Family
152 if (((par->Chipset & 0xfff0) == 0x0290) || in nvGetClocks()153 ((par->Chipset & 0xfff0) == 0x0390)) { in nvGetClocks()200 if (((par->Chipset & 0x0ff0) == 0x0300) || in nvGetClocks()201 ((par->Chipset & 0x0ff0) == 0x0330)) { in nvGetClocks()688 if ((par->Chipset & 0x0FF0) == 0x01A0) { in nForceUpdateArbitrationSettings()904 if ((par->Chipset & 0xfff0) == 0x0240 || in NVCalcStateExt()905 (par->Chipset & 0xfff0) == 0x03d0) { in NVCalcStateExt()908 } else if (((par->Chipset & 0xffff) == 0x01A0) || in NVCalcStateExt()909 ((par->Chipset & 0xffff) == 0x01f0)) { in NVCalcStateExt()963 (par->Chipset & 0xfff0) == 0x0040) { in NVLoadStateExt()[all …]
233 u32 implementation = par->Chipset & 0x0ff0; in nv10GetConfig()245 if ((par->Chipset & 0xffff) == 0x01a0) { in nv10GetConfig()250 } else if ((par->Chipset & 0xffff) == 0x01f0) { in nv10GetConfig()278 u16 implementation = par->Chipset & 0x0ff0; in NVCommonSetup()328 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020); in NVCommonSetup()331 switch (par->Chipset & 0xffff) { in NVCommonSetup()411 if ((par->Chipset & 0x0fff) <= 0x0020) in NVCommonSetup()
176 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { in nvidia_panel_tweak()181 if ((par->Chipset & 0xfff0) == 0x0310) in nvidia_panel_tweak()461 if ((par->Chipset & 0x0ff0) != 0x0110) in nvidia_calc_regs()470 if ((par->Chipset & 0x0ff0) == 0x0110) { in nvidia_calc_regs()618 if ((par->Chipset & 0x0ff0) == 0x0110) in nvidiafb_set_par()1227 switch (par->Chipset & 0x0ff0) { in nvidia_get_arch()1332 par->Chipset = nvidia_get_chipset(info); in nvidiafb_probe()
106 int Chipset; member
103 switch(par->Chipset & 0xffff) { in riva_is_second()159 unsigned int chipset = par->Chipset; in riva_get_memlen()341 switch (par->Chipset & 0xffff) { in riva_common_setup()377 switch (par->Chipset & 0x0ff0) { in riva_common_setup()379 if (par->Chipset == NV_CHIP_GEFORCE2_GO) in riva_common_setup()421 RivaGetConfig(&par->riva, par->pdev, par->Chipset); in riva_common_setup()
59 unsigned int Chipset; member
1298 if((chip->Chipset == NV_CHIP_IGEFORCE2) || in CalcStateExt()1299 (chip->Chipset == NV_CHIP_0x01F0)) in CalcStateExt()1647 if((chip->Chipset & 0x0ff0) == 0x0110) { in LoadStateExt()1650 if((chip->Chipset & 0x0ff0) >= 0x0170) { in LoadStateExt()1803 if((chip->Chipset & 0x0ff0) == 0x0110) { in UnloadStateExt()1806 if((chip->Chipset & 0x0ff0) >= 0x0170) { in UnloadStateExt()2240 chip->Chipset = chipset; in RivaGetConfig()
428 U032 Chipset; member
1928 default_par->Chipset = (pd->vendor << 16) | pd->device; in rivafb_probe()1929 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); in rivafb_probe()
23 Chipset.
54 - qcom,dll-config: Chipset and Platform specific value. Use this field to
6 SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
12 SoC/Chipset to appear only in ACPI namespace. These are typically devices
625 ICU02F0 "Gateway Ethertwist 16 (Fujitsu Chipset)"626 ICU02F1 "Gateway Ethertwist 16 (National Chipset)"627 ICU0300 "Gateway Ethertwist PC/PC-WS(National Chipset)"
322 tristate "Generic PCI IDE Chipset Support"
687 tristate "Intel(R) C600 Series Chipset SAS Controller"
1192 model Type/Chipset of IDE controller
1495 D: Active-ATA-Chipset maddness..........
