Searched refs:CSR0_TINT (Results 1 – 6 of 6) sorted by relevance
25 #define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */ macro
37 #define CSR0_TINT 0x0200 macro
244 …write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0… in am79c961_init_for_open()595 (CSR0_IENA|CSR0_TINT|CSR0_RINT| in am79c961_interrupt()602 if (status & CSR0_TINT) { in am79c961_interrupt()614 } while (--n && status & (CSR0_RINT | CSR0_TINT)); in am79c961_interrupt()
221 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ macro668 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON); in lance_interrupt()678 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ in lance_interrupt()760 if(DREG & (CSR0_RINT | CSR0_TINT)) { in lance_interrupt()
321 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ macro869 while( ((csr0 = DREG) & (CSR0_ERR | CSR0_TINT | CSR0_RINT)) && in lance_interrupt()882 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ in lance_interrupt()
891 if(!(csr0 & (CSR0_ERR | CSR0_RINT | CSR0_TINT))) in ni65_interrupt()896 if(csr0 & CSR0_TINT) /* XMIT-int? */ in ni65_interrupt()
