Searched refs:CP0 (Results 1 – 8 of 8) sorted by relevance
104 /* CON6 on CP0 expansion */111 /* CON5 on CP0 expansion */142 /* CON4 on CP0 expansion */156 /* CON9 on CP0 expansion */169 /* CON10 on CP0 expansion */
144 * [35-38] CP0 I2C1 and I2C0314 * [29] CP0 10G SFP TX Disable
75 @ CP0 and CP1 accessible?79 @ enable access to CP0 and CP1209 @ enable access to CP0 and CP1223 @ disable access to CP0 and CP1324 @ CP0 and CP1 accessible?
621 /* CP0 VDD & VCS : IR35221 */622 /* CP0 VDN : IR35221 */623 /* CP0 VIO : IR38064 */624 /* CP0 VDDR : PXM1330 */641 /* CP0 VDD & VCS : IR35221 */642 /* CP0 VDN : IR35221 */643 /* CP0 VIO : IR38064 */644 /* CP0 VDDR : PXM1330 */
524 /* CP0 VDD & VCS : IR35221 */525 /* CP0 VDN & VIO : IR35221 */526 /* CP0 VDDR : IR35221 */
850 #define CP0 (1 << 0) macro
3526 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
2499 MIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit
