Searched refs:CNL_PORT_CL1CM_DW5 (Results 1 – 3 of 3) sorted by relevance
145 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, in cnl_combo_phy_verify_state()166 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); in cnl_combo_phys_init()168 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); in cnl_combo_phys_init()
2427 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); in cnl_ddi_vswing_sequence()2429 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); in cnl_ddi_vswing_sequence()
1883 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) macro
