Searched refs:CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 (Results 1 – 5 of 5) sorted by relevance
50 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 macro60 #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
87 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: in get_pcie_lane_support()
4805 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()4813 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()4820 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()4826 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()4831 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()4835 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); in amdgpu_device_get_pcie_info()4838 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; in amdgpu_device_get_pcie_info()
1001 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) in smu_smc_hw_setup()
857 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) in vega20_override_pcie_parameters()
