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Searched refs:BIT0 (Results 1 – 25 of 59) sorted by relevance

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/Linux-v5.10/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h44 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b…
49 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB …
51 …{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0…
52 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
55 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling unti…
56 …_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
61 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR …
72 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
77 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b…
88 … PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO sus…
[all …]
Dhal_com_reg.h560 #define HSIMR_GPIO12_0_INT_EN BIT0
569 #define HSISR_GPIO12_0_INT BIT0
608 #define RRSR_1M BIT0
633 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
759 #define WOW_PMEN BIT0 /* Power management Enable. */
804 #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */
815 #define IMR_WLANOFF BIT0
852 #define PHIMR_ROK BIT0 /* Receive DMA OK Interrupt */
903 #define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */
957 #define IMR_ROK_88E BIT0 /* Receive DMA OK */
[all …]
Drtw_ht.h68 #define LDPC_HT_ENABLE_RX BIT0
73 #define STBC_HT_ENABLE_RX BIT0
78 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
Drtl8723b_spec.h226 #define IMR_ROK_8723B BIT0 /* Receive DMA OK */
Dhal_phy.h38 #define ANT_DETECT_BY_SINGLE_TONE BIT0
/Linux-v5.10/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
371 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
389 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
[all …]
/Linux-v5.10/drivers/video/fbdev/via/
Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
563 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
585 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
652 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
654 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
661 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
670 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
746 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
846 bdithering = BIT0; in fill_lcd_format()
[all …]
Dvia_utility.c152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dhw.c472 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
949 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
986 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
987 get_bit = (timing_value & (BIT0 << bit_num)); in viafb_load_reg()
1667 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1681 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1688 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
/Linux-v5.10/drivers/scsi/
Ddc395x.h76 #define BIT0 0x00000001 macro
79 #define UNIT_ALLOCATED BIT0
85 #define DASD_SUPPORT BIT0
121 #define RESET_DEV BIT0
126 #define ABORT_DEV_ BIT0
129 #define SRB_OK BIT0
143 #define AUTO_REQSENSE BIT0
174 #define SYNC_NEGO_ENABLE BIT0
630 #define MORE2_DRV BIT0
/Linux-v5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
149 #define RCR_AAP BIT0
201 #define SCR_TxUseDK BIT0
228 #define IMR_ROK BIT0
231 #define TPPoll_BKQ BIT0
271 #define AcmHw_HwEn BIT0
279 #define AcmFw_BeqStatus BIT0
332 #define BW_OPMODE_11J BIT0
361 #define RRSR_1M BIT0
/Linux-v5.10/drivers/staging/rtl8723bs/core/
Drtw_odm.c103 (BIT0 << i) & dbg_comp ? '+' : ' ', in rtw_odm_dbg_comp_msg()
142 (BIT0 << i) & ability ? '+' : ' ', i, in rtw_odm_ability_msg()
/Linux-v5.10/drivers/staging/rtl8723bs/hal/
Dodm_DIG.h92 ODM_PAUSE_DIG = BIT0,
97 ODM_PAUSE_CCKPD = BIT0,
DHalBtc8723b1Ant.h15 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dodm_reg.h93 #define BIT_FA_RESET BIT0
DHalBtcOutSrc.h89 #define INTF_INIT BIT0
93 #define ALGO_BT_RSSI_STATE BIT0
105 #define WIFI_STA_CONNECTED BIT0
Dodm_debug.h61 #define ODM_COMP_DIG BIT0
Dodm.h422 ODM_BB_DIG = BIT0,
485 ODM_RF_TX_A = BIT0,
531 ODM_NO_LINK = BIT0,
545 ODM_WM_B = BIT0,
/Linux-v5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtc8821a1ant.h15 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtc8723b1ant.h14 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
17 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbt_precomp.h31 #define BIT0 0x00000001 macro
Dhalbtcoutsrc.h88 #define INTF_INIT BIT0
92 #define ALGO_BT_RSSI_STATE BIT0
104 #define WIFI_STA_CONNECTED BIT0
/Linux-v5.10/drivers/tty/
Dsynclink_gt.c214 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
221 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
382 #define MASK_FRAMING BIT0
424 #define IRQ_MASTER BIT0
1844 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1848 else if (status & BIT0) in rx_async()
1855 else if (status & BIT0) in rx_async()
2068 if (status & BIT0) { in ri_change()
3871 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3884 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
[all …]
/Linux-v5.10/drivers/staging/rtl8192e/
Drtl819x_Qos.h10 #define BIT0 0x00000001 macro

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