Searched refs:AXI_MASTER_CFG_BASE (Results 1 – 2 of 2) sorted by relevance
279 #define AXI_MASTER_CFG_BASE (0x5000) macro1434 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN); in axi_bus_is_idle_v2_hw()1496 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_phy_v2_hw()1499 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_phy_v2_hw()1533 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_phy_v2_hw()3436 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); in soft_reset_v2_hw()3442 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN); in soft_reset_v2_hw()
312 #define AXI_MASTER_CFG_BASE (0x5000) macro2092 AXI_MASTER_CFG_BASE + in fatal_axi_int_v3_hw()2095 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in fatal_axi_int_v3_hw()2543 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_host_v3_hw()2546 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_host_v3_hw()2550 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + in disable_host_v3_hw()2911 .base_off = AXI_MASTER_CFG_BASE,
