Searched refs:AR_CH0_DPLL2_KD (Results 1 – 2 of 2) sorted by relevance
1297 #define AR_CH0_DPLL2_KD 0x03F80000 macro
773 AR_CH0_DPLL2_KD, 0x40); in ath9k_hw_init_pll()826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); in ath9k_hw_init_pll()
