Searched refs:AMDGPU_UVD_FIRMWARE_OFFSET (Results 1 – 10 of 10) sorted by relevance
32 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 macro38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
545 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
242 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
410 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_mc_resume()476 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()1213 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_sriov_start()
262 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v5_0_mc_resume()
445 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_mc_resume()501 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()1301 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_start_sriov()
311 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v1_0_mc_resume_spg_mode()381 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
676 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_mc_resume()818 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_sriov_start()
345 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_0_mc_resume()413 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
592 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v6_0_mc_resume()
