1 /*
2 * R8A77970 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 */
17
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20
21 #include "core.h"
22 #include "sh_pfc.h"
23
24 #define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_28(1, fn, sfx), \
27 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_6(4, fn, sfx), \
30 PORT_GP_15(5, fn, sfx)
31 /*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36 /* GPSR0 */
37 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
38 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
39 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
40 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
41 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
42 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
43 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
44 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
45 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
46 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
47 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
48 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
49 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
50 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
51 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
52 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
53 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
54 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
55 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
56 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
57 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
58 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
59
60 /* GPSR1 */
61 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
62 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
63 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
64 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
65 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
66 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
67 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
68 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
69 #define GPSR1_19 FM(AVB0_AVTP_MATCH)
70 #define GPSR1_18 FM(AVB0_LINK)
71 #define GPSR1_17 FM(AVB0_PHY_INT)
72 #define GPSR1_16 FM(AVB0_MAGIC)
73 #define GPSR1_15 FM(AVB0_MDC)
74 #define GPSR1_14 FM(AVB0_MDIO)
75 #define GPSR1_13 FM(AVB0_TXCREFCLK)
76 #define GPSR1_12 FM(AVB0_TD3)
77 #define GPSR1_11 FM(AVB0_TD2)
78 #define GPSR1_10 FM(AVB0_TD1)
79 #define GPSR1_9 FM(AVB0_TD0)
80 #define GPSR1_8 FM(AVB0_TXC)
81 #define GPSR1_7 FM(AVB0_TX_CTL)
82 #define GPSR1_6 FM(AVB0_RD3)
83 #define GPSR1_5 FM(AVB0_RD2)
84 #define GPSR1_4 FM(AVB0_RD1)
85 #define GPSR1_3 FM(AVB0_RD0)
86 #define GPSR1_2 FM(AVB0_RXC)
87 #define GPSR1_1 FM(AVB0_RX_CTL)
88 #define GPSR1_0 F_(IRQ0, IP2_27_24)
89
90 /* GPSR2 */
91 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
92 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
93 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
94 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
95 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
96 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
97 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
98 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
99 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
100 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
101 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
102 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
103 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
104 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
105 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
106 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
107 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
108
109 /* GPSR3 */
110 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
111 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
112 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
113 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
114 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
115 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
116 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
117 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
118 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
119 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
120 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
121 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
122 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
123 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
124 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
125 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
126 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
127
128 /* GPSR4 */
129 #define GPSR4_5 F_(SDA2, IP7_27_24)
130 #define GPSR4_4 F_(SCL2, IP7_23_20)
131 #define GPSR4_3 F_(SDA1, IP7_19_16)
132 #define GPSR4_2 F_(SCL1, IP7_15_12)
133 #define GPSR4_1 F_(SDA0, IP7_11_8)
134 #define GPSR4_0 F_(SCL0, IP7_7_4)
135
136 /* GPSR5 */
137 #define GPSR5_14 FM(RPC_INT_N)
138 #define GPSR5_13 FM(RPC_WP_N)
139 #define GPSR5_12 FM(RPC_RESET_N)
140 #define GPSR5_11 FM(QSPI1_SSL)
141 #define GPSR5_10 FM(QSPI1_IO3)
142 #define GPSR5_9 FM(QSPI1_IO2)
143 #define GPSR5_8 FM(QSPI1_MISO_IO1)
144 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
145 #define GPSR5_6 FM(QSPI1_SPCLK)
146 #define GPSR5_5 FM(QSPI0_SSL)
147 #define GPSR5_4 FM(QSPI0_IO3)
148 #define GPSR5_3 FM(QSPI0_IO2)
149 #define GPSR5_2 FM(QSPI0_MISO_IO1)
150 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
151 #define GPSR5_0 FM(QSPI0_SPCLK)
152
153
154 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
155 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
158 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
159 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
160 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
161 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
162 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
163 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177 #define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227
228 #define PINMUX_GPSR \
229 \
230 GPSR1_27 \
231 GPSR1_26 \
232 GPSR1_25 \
233 GPSR1_24 \
234 GPSR1_23 \
235 GPSR1_22 \
236 GPSR0_21 GPSR1_21 \
237 GPSR0_20 GPSR1_20 \
238 GPSR0_19 GPSR1_19 \
239 GPSR0_18 GPSR1_18 \
240 GPSR0_17 GPSR1_17 \
241 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
242 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
243 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
244 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
245 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
246 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
247 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
248 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
249 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
250 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
251 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
252 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
253 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
254 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
255 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
256 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
257 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
258
259 #define PINMUX_IPSR \
260 \
261 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
262 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
263 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
264 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
265 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
266 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
267 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
268 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
269 \
270 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
271 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
272 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
273 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
274 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
275 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
276 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
277 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
278 \
279 FM(IP8_3_0) IP8_3_0 \
280 FM(IP8_7_4) IP8_7_4 \
281 FM(IP8_11_8) IP8_11_8 \
282 FM(IP8_15_12) IP8_15_12 \
283 FM(IP8_19_16) IP8_19_16 \
284 FM(IP8_23_20) IP8_23_20 \
285 FM(IP8_27_24) IP8_27_24 \
286 FM(IP8_31_28) IP8_31_28
287
288 /* MOD_SEL0 */ /* 0 */ /* 1 */
289 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
290 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
291 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
292 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
293 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
294 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
295 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
296 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
297 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
298 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
299 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
300 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
301
302 #define PINMUX_MOD_SELS \
303 \
304 MOD_SEL0_11 \
305 MOD_SEL0_10 \
306 MOD_SEL0_9 \
307 MOD_SEL0_8 \
308 MOD_SEL0_7 \
309 MOD_SEL0_6 \
310 MOD_SEL0_5 \
311 MOD_SEL0_4 \
312 MOD_SEL0_3 \
313 MOD_SEL0_2 \
314 MOD_SEL0_1 \
315 MOD_SEL0_0
316
317 enum {
318 PINMUX_RESERVED = 0,
319
320 PINMUX_DATA_BEGIN,
321 GP_ALL(DATA),
322 PINMUX_DATA_END,
323
324 #define F_(x, y)
325 #define FM(x) FN_##x,
326 PINMUX_FUNCTION_BEGIN,
327 GP_ALL(FN),
328 PINMUX_GPSR
329 PINMUX_IPSR
330 PINMUX_MOD_SELS
331 PINMUX_FUNCTION_END,
332 #undef F_
333 #undef FM
334
335 #define F_(x, y)
336 #define FM(x) x##_MARK,
337 PINMUX_MARK_BEGIN,
338 PINMUX_GPSR
339 PINMUX_IPSR
340 PINMUX_MOD_SELS
341 PINMUX_MARK_END,
342 #undef F_
343 #undef FM
344 };
345
346 static const u16 pinmux_data[] = {
347 PINMUX_DATA_GP_ALL(),
348
349 PINMUX_SINGLE(AVB0_RX_CTL),
350 PINMUX_SINGLE(AVB0_RXC),
351 PINMUX_SINGLE(AVB0_RD0),
352 PINMUX_SINGLE(AVB0_RD1),
353 PINMUX_SINGLE(AVB0_RD2),
354 PINMUX_SINGLE(AVB0_RD3),
355 PINMUX_SINGLE(AVB0_TX_CTL),
356 PINMUX_SINGLE(AVB0_TXC),
357 PINMUX_SINGLE(AVB0_TD0),
358 PINMUX_SINGLE(AVB0_TD1),
359 PINMUX_SINGLE(AVB0_TD2),
360 PINMUX_SINGLE(AVB0_TD3),
361 PINMUX_SINGLE(AVB0_TXCREFCLK),
362 PINMUX_SINGLE(AVB0_MDIO),
363 PINMUX_SINGLE(AVB0_MDC),
364 PINMUX_SINGLE(AVB0_MAGIC),
365 PINMUX_SINGLE(AVB0_PHY_INT),
366 PINMUX_SINGLE(AVB0_LINK),
367 PINMUX_SINGLE(AVB0_AVTP_MATCH),
368
369 PINMUX_SINGLE(QSPI0_SPCLK),
370 PINMUX_SINGLE(QSPI0_MOSI_IO0),
371 PINMUX_SINGLE(QSPI0_MISO_IO1),
372 PINMUX_SINGLE(QSPI0_IO2),
373 PINMUX_SINGLE(QSPI0_IO3),
374 PINMUX_SINGLE(QSPI0_SSL),
375 PINMUX_SINGLE(QSPI1_SPCLK),
376 PINMUX_SINGLE(QSPI1_MOSI_IO0),
377 PINMUX_SINGLE(QSPI1_MISO_IO1),
378 PINMUX_SINGLE(QSPI1_IO2),
379 PINMUX_SINGLE(QSPI1_IO3),
380 PINMUX_SINGLE(QSPI1_SSL),
381 PINMUX_SINGLE(RPC_RESET_N),
382 PINMUX_SINGLE(RPC_WP_N),
383 PINMUX_SINGLE(RPC_INT_N),
384
385 /* IPSR0 */
386 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
387 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
388 PINMUX_IPSR_GPSR(IP0_3_0, A0),
389
390 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
391 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
392 PINMUX_IPSR_GPSR(IP0_7_4, A1),
393
394 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
395 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
396 PINMUX_IPSR_GPSR(IP0_11_8, A2),
397
398 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
399 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
400 PINMUX_IPSR_GPSR(IP0_15_12, A3),
401
402 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
403 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
404 PINMUX_IPSR_GPSR(IP0_19_16, A4),
405
406 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
407 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
408 PINMUX_IPSR_GPSR(IP0_23_20, A5),
409
410 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
411 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
412 PINMUX_IPSR_GPSR(IP0_27_24, A6),
413
414 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
415 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
416 PINMUX_IPSR_GPSR(IP0_31_28, A7),
417 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
418
419 /* IPSR1 */
420 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
421 PINMUX_IPSR_GPSR(IP1_3_0, A8),
422 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
423
424 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
425 PINMUX_IPSR_GPSR(IP1_7_4, A9),
426 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
427
428 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
429 PINMUX_IPSR_GPSR(IP1_11_8, A10),
430 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
431
432 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
433 PINMUX_IPSR_GPSR(IP1_15_12, A11),
434 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
435
436 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
437 PINMUX_IPSR_GPSR(IP1_19_16, A12),
438 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
439
440 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
441 PINMUX_IPSR_GPSR(IP1_23_20, A13),
442 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
443
444 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
445 PINMUX_IPSR_GPSR(IP1_27_24, A14),
446 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
447
448 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
449 PINMUX_IPSR_GPSR(IP1_31_28, A15),
450 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
451
452 /* IPSR2 */
453 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
454 PINMUX_IPSR_GPSR(IP2_3_0, A16),
455 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
456
457 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
458 PINMUX_IPSR_GPSR(IP2_7_4, A17),
459
460 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
461 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
462 PINMUX_IPSR_GPSR(IP2_11_8, A18),
463
464 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
465 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
466 PINMUX_IPSR_GPSR(IP2_15_12, A19),
467 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
468
469 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
470 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
471
472 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
473 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
474
475 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
476 PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
477
478 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
479 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
480 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
481 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
482
483 /* IPSR3 */
484 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
485 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
486 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
487 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
488 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
489
490 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
491 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
492 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
493 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
494
495 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
496 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
497 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
498 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
499
500 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
501 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
502 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
503 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
504
505 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
506 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
507 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
508 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
509
510 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
511 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
512 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
513
514 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
515 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
516 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
517
518 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
519 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
520 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
521
522 /* IPSR4 */
523 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
524 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
525 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
526
527 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
528 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
529 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
530
531 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
532 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
533 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
534
535 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
536 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
537 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
538
539 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
540 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
541 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
542 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
543
544 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
545 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
546 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
547 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
548
549 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
550 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
551 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
552 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
553
554 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
555 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
556 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
557 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
558 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
559
560 /* IPSR5 */
561 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
562 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
563 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
564
565 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
566 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
567 PINMUX_IPSR_GPSR(IP5_7_4, D0),
568
569 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
570 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
571 PINMUX_IPSR_GPSR(IP5_11_8, D1),
572
573 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
574 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
575 PINMUX_IPSR_GPSR(IP5_15_12, D2),
576
577 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
578 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
579 PINMUX_IPSR_GPSR(IP5_19_16, D3),
580
581 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
582 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
583 PINMUX_IPSR_GPSR(IP5_23_20, D4),
584 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
585
586 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
587 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
588 PINMUX_IPSR_GPSR(IP5_27_24, D5),
589 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
590
591 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
592 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
593 PINMUX_IPSR_GPSR(IP5_31_28, D6),
594 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
595
596 /* IPSR6 */
597 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
598 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
599 PINMUX_IPSR_GPSR(IP6_3_0, D7),
600 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
601
602 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
603 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
604 PINMUX_IPSR_GPSR(IP6_7_4, D8),
605 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
606
607 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
608 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
609 PINMUX_IPSR_GPSR(IP6_11_8, D9),
610 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
611
612 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
613 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
614 PINMUX_IPSR_GPSR(IP6_15_12, D10),
615 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
616
617 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
618 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
619 PINMUX_IPSR_GPSR(IP6_19_16, D11),
620 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
621
622 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
623 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
624 PINMUX_IPSR_GPSR(IP6_23_20, D12),
625 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
626 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
627
628 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
629 PINMUX_IPSR_GPSR(IP6_27_24, D13),
630 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
631 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
632
633 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
634 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
635 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
636 PINMUX_IPSR_GPSR(IP6_31_28, D14),
637 PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
638
639 /* IPSR7 */
640 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
641 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
642 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
643 PINMUX_IPSR_GPSR(IP7_3_0, D15),
644 PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
645
646 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
647 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
648 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
649 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
650 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
651
652 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
653 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
654 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
655 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
656 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
657 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
658
659 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
660 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
661 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
662 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
663 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
664 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
665
666 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
667 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
668 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
669 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
670 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
671 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
672
673 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
674 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
675 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
676 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
677 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
678 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
679
680 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
681 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
682 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
683 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
684 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
685 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
686
687 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
688 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
689
690 /* IPSR8 */
691 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
692 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
693 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
694 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
695 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
696
697 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
698 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
699 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
700 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
701
702 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
703 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
704 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
705 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
706 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
707
708 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
709 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
710 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
711 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
712 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
713
714 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
715 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
716 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
717 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
718 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
719
720 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
721 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
722
723 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
724 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
725 };
726
727 static const struct sh_pfc_pin pinmux_pins[] = {
728 PINMUX_GPIO_GP_ALL(),
729 };
730
731 /* - AVB0 ------------------------------------------------------------------- */
732 static const unsigned int avb0_link_pins[] = {
733 /* AVB0_LINK */
734 RCAR_GP_PIN(1, 18),
735 };
736 static const unsigned int avb0_link_mux[] = {
737 AVB0_LINK_MARK,
738 };
739 static const unsigned int avb0_magic_pins[] = {
740 /* AVB0_MAGIC */
741 RCAR_GP_PIN(1, 16),
742 };
743 static const unsigned int avb0_magic_mux[] = {
744 AVB0_MAGIC_MARK,
745 };
746 static const unsigned int avb0_phy_int_pins[] = {
747 /* AVB0_PHY_INT */
748 RCAR_GP_PIN(1, 17),
749 };
750 static const unsigned int avb0_phy_int_mux[] = {
751 AVB0_PHY_INT_MARK,
752 };
753 static const unsigned int avb0_mdio_pins[] = {
754 /* AVB0_MDC, AVB0_MDIO */
755 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
756 };
757 static const unsigned int avb0_mdio_mux[] = {
758 AVB0_MDC_MARK, AVB0_MDIO_MARK,
759 };
760 static const unsigned int avb0_rgmii_pins[] = {
761 /*
762 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
763 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
764 */
765 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
766 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
767 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
768 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
769 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
770 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
771 };
772 static const unsigned int avb0_rgmii_mux[] = {
773 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
774 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
775 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
776 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
777 };
778 static const unsigned int avb0_txcrefclk_pins[] = {
779 /* AVB0_TXCREFCLK */
780 RCAR_GP_PIN(1, 13),
781 };
782 static const unsigned int avb0_txcrefclk_mux[] = {
783 AVB0_TXCREFCLK_MARK,
784 };
785 static const unsigned int avb0_avtp_pps_pins[] = {
786 /* AVB0_AVTP_PPS */
787 RCAR_GP_PIN(2, 6),
788 };
789 static const unsigned int avb0_avtp_pps_mux[] = {
790 AVB0_AVTP_PPS_MARK,
791 };
792 static const unsigned int avb0_avtp_capture_pins[] = {
793 /* AVB0_AVTP_CAPTURE */
794 RCAR_GP_PIN(1, 20),
795 };
796 static const unsigned int avb0_avtp_capture_mux[] = {
797 AVB0_AVTP_CAPTURE_MARK,
798 };
799 static const unsigned int avb0_avtp_match_pins[] = {
800 /* AVB0_AVTP_MATCH */
801 RCAR_GP_PIN(1, 19),
802 };
803 static const unsigned int avb0_avtp_match_mux[] = {
804 AVB0_AVTP_MATCH_MARK,
805 };
806
807 /* - CANFD Clock ------------------------------------------------------------ */
808 static const unsigned int canfd_clk_a_pins[] = {
809 /* CANFD_CLK */
810 RCAR_GP_PIN(1, 25),
811 };
812 static const unsigned int canfd_clk_a_mux[] = {
813 CANFD_CLK_A_MARK,
814 };
815 static const unsigned int canfd_clk_b_pins[] = {
816 /* CANFD_CLK */
817 RCAR_GP_PIN(3, 8),
818 };
819 static const unsigned int canfd_clk_b_mux[] = {
820 CANFD_CLK_B_MARK,
821 };
822
823 /* - CANFD0 ----------------------------------------------------------------- */
824 static const unsigned int canfd0_data_a_pins[] = {
825 /* TX, RX */
826 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
827 };
828 static const unsigned int canfd0_data_a_mux[] = {
829 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
830 };
831 static const unsigned int canfd0_data_b_pins[] = {
832 /* TX, RX */
833 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
834 };
835 static const unsigned int canfd0_data_b_mux[] = {
836 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
837 };
838
839 /* - CANFD1 ----------------------------------------------------------------- */
840 static const unsigned int canfd1_data_pins[] = {
841 /* TX, RX */
842 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
843 };
844 static const unsigned int canfd1_data_mux[] = {
845 CANFD1_TX_MARK, CANFD1_RX_MARK,
846 };
847
848 /* - DU --------------------------------------------------------------------- */
849 static const unsigned int du_rgb666_pins[] = {
850 /* R[7:2], G[7:2], B[7:2] */
851 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
852 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
853 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
854 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
855 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
856 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
857 };
858 static const unsigned int du_rgb666_mux[] = {
859 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
860 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
861 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
862 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
863 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
864 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
865 };
866 static const unsigned int du_clk_out_pins[] = {
867 /* DOTCLKOUT */
868 RCAR_GP_PIN(0, 18),
869 };
870 static const unsigned int du_clk_out_mux[] = {
871 DU_DOTCLKOUT_MARK,
872 };
873 static const unsigned int du_sync_pins[] = {
874 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
875 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
876 };
877 static const unsigned int du_sync_mux[] = {
878 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
879 };
880 static const unsigned int du_oddf_pins[] = {
881 /* EXODDF/ODDF/DISP/CDE */
882 RCAR_GP_PIN(0, 21),
883 };
884 static const unsigned int du_oddf_mux[] = {
885 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
886 };
887 static const unsigned int du_cde_pins[] = {
888 /* CDE */
889 RCAR_GP_PIN(1, 22),
890 };
891 static const unsigned int du_cde_mux[] = {
892 DU_CDE_MARK,
893 };
894 static const unsigned int du_disp_pins[] = {
895 /* DISP */
896 RCAR_GP_PIN(1, 21),
897 };
898 static const unsigned int du_disp_mux[] = {
899 DU_DISP_MARK,
900 };
901
902 /* - HSCIF0 ----------------------------------------------------------------- */
903 static const unsigned int hscif0_data_pins[] = {
904 /* HRX, HTX */
905 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
906 };
907 static const unsigned int hscif0_data_mux[] = {
908 HRX0_MARK, HTX0_MARK,
909 };
910 static const unsigned int hscif0_clk_pins[] = {
911 /* HSCK */
912 RCAR_GP_PIN(0, 0),
913 };
914 static const unsigned int hscif0_clk_mux[] = {
915 HSCK0_MARK,
916 };
917 static const unsigned int hscif0_ctrl_pins[] = {
918 /* HRTS#, HCTS# */
919 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
920 };
921 static const unsigned int hscif0_ctrl_mux[] = {
922 HRTS0_N_MARK, HCTS0_N_MARK,
923 };
924
925 /* - HSCIF1 ----------------------------------------------------------------- */
926 static const unsigned int hscif1_data_pins[] = {
927 /* HRX, HTX */
928 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
929 };
930 static const unsigned int hscif1_data_mux[] = {
931 HRX1_MARK, HTX1_MARK,
932 };
933 static const unsigned int hscif1_clk_pins[] = {
934 /* HSCK */
935 RCAR_GP_PIN(2, 7),
936 };
937 static const unsigned int hscif1_clk_mux[] = {
938 HSCK1_MARK,
939 };
940 static const unsigned int hscif1_ctrl_pins[] = {
941 /* HRTS#, HCTS# */
942 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
943 };
944 static const unsigned int hscif1_ctrl_mux[] = {
945 HRTS1_N_MARK, HCTS1_N_MARK,
946 };
947
948 /* - HSCIF2 ----------------------------------------------------------------- */
949 static const unsigned int hscif2_data_pins[] = {
950 /* HRX, HTX */
951 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
952 };
953 static const unsigned int hscif2_data_mux[] = {
954 HRX2_MARK, HTX2_MARK,
955 };
956 static const unsigned int hscif2_clk_pins[] = {
957 /* HSCK */
958 RCAR_GP_PIN(2, 12),
959 };
960 static const unsigned int hscif2_clk_mux[] = {
961 HSCK2_MARK,
962 };
963 static const unsigned int hscif2_ctrl_pins[] = {
964 /* HRTS#, HCTS# */
965 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
966 };
967 static const unsigned int hscif2_ctrl_mux[] = {
968 HRTS2_N_MARK, HCTS2_N_MARK,
969 };
970
971 /* - HSCIF3 ----------------------------------------------------------------- */
972 static const unsigned int hscif3_data_pins[] = {
973 /* HRX, HTX */
974 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
975 };
976 static const unsigned int hscif3_data_mux[] = {
977 HRX3_MARK, HTX3_MARK,
978 };
979 static const unsigned int hscif3_clk_pins[] = {
980 /* HSCK */
981 RCAR_GP_PIN(2, 0),
982 };
983 static const unsigned int hscif3_clk_mux[] = {
984 HSCK3_MARK,
985 };
986 static const unsigned int hscif3_ctrl_pins[] = {
987 /* HRTS#, HCTS# */
988 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
989 };
990 static const unsigned int hscif3_ctrl_mux[] = {
991 HRTS3_N_MARK, HCTS3_N_MARK,
992 };
993
994 /* - I2C0 ------------------------------------------------------------------- */
995 static const unsigned int i2c0_pins[] = {
996 /* SDA, SCL */
997 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
998 };
999 static const unsigned int i2c0_mux[] = {
1000 SDA0_MARK, SCL0_MARK,
1001 };
1002
1003 /* - I2C1 ------------------------------------------------------------------- */
1004 static const unsigned int i2c1_pins[] = {
1005 /* SDA, SCL */
1006 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1007 };
1008 static const unsigned int i2c1_mux[] = {
1009 SDA1_MARK, SCL1_MARK,
1010 };
1011
1012 /* - I2C2 ------------------------------------------------------------------- */
1013 static const unsigned int i2c2_pins[] = {
1014 /* SDA, SCL */
1015 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1016 };
1017 static const unsigned int i2c2_mux[] = {
1018 SDA2_MARK, SCL2_MARK,
1019 };
1020
1021 /* - I2C3 ------------------------------------------------------------------- */
1022 static const unsigned int i2c3_a_pins[] = {
1023 /* SDA, SCL */
1024 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1025 };
1026 static const unsigned int i2c3_a_mux[] = {
1027 SDA3_A_MARK, SCL3_A_MARK,
1028 };
1029 static const unsigned int i2c3_b_pins[] = {
1030 /* SDA, SCL */
1031 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1032 };
1033 static const unsigned int i2c3_b_mux[] = {
1034 SDA3_B_MARK, SCL3_B_MARK,
1035 };
1036
1037 /* - I2C4 ------------------------------------------------------------------- */
1038 static const unsigned int i2c4_pins[] = {
1039 /* SDA, SCL */
1040 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1041 };
1042 static const unsigned int i2c4_mux[] = {
1043 SDA4_MARK, SCL4_MARK,
1044 };
1045
1046 /* - INTC-EX ---------------------------------------------------------------- */
1047 static const unsigned int intc_ex_irq0_pins[] = {
1048 /* IRQ0 */
1049 RCAR_GP_PIN(1, 0),
1050 };
1051 static const unsigned int intc_ex_irq0_mux[] = {
1052 IRQ0_MARK,
1053 };
1054 static const unsigned int intc_ex_irq1_pins[] = {
1055 /* IRQ1 */
1056 RCAR_GP_PIN(0, 11),
1057 };
1058 static const unsigned int intc_ex_irq1_mux[] = {
1059 IRQ1_MARK,
1060 };
1061 static const unsigned int intc_ex_irq2_pins[] = {
1062 /* IRQ2 */
1063 RCAR_GP_PIN(0, 12),
1064 };
1065 static const unsigned int intc_ex_irq2_mux[] = {
1066 IRQ2_MARK,
1067 };
1068 static const unsigned int intc_ex_irq3_pins[] = {
1069 /* IRQ3 */
1070 RCAR_GP_PIN(0, 19),
1071 };
1072 static const unsigned int intc_ex_irq3_mux[] = {
1073 IRQ3_MARK,
1074 };
1075 static const unsigned int intc_ex_irq4_pins[] = {
1076 /* IRQ4 */
1077 RCAR_GP_PIN(3, 15),
1078 };
1079 static const unsigned int intc_ex_irq4_mux[] = {
1080 IRQ4_MARK,
1081 };
1082 static const unsigned int intc_ex_irq5_pins[] = {
1083 /* IRQ5 */
1084 RCAR_GP_PIN(3, 16),
1085 };
1086 static const unsigned int intc_ex_irq5_mux[] = {
1087 IRQ5_MARK,
1088 };
1089
1090 /* - MMC -------------------------------------------------------------------- */
1091 static const unsigned int mmc_data1_pins[] = {
1092 /* D0 */
1093 RCAR_GP_PIN(3, 6),
1094 };
1095 static const unsigned int mmc_data1_mux[] = {
1096 MMC_D0_MARK,
1097 };
1098 static const unsigned int mmc_data4_pins[] = {
1099 /* D[0:3] */
1100 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1101 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1102 };
1103 static const unsigned int mmc_data4_mux[] = {
1104 MMC_D0_MARK, MMC_D1_MARK,
1105 MMC_D2_MARK, MMC_D3_MARK,
1106 };
1107 static const unsigned int mmc_data8_pins[] = {
1108 /* D[0:7] */
1109 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1110 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1111 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1112 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1113 };
1114 static const unsigned int mmc_data8_mux[] = {
1115 MMC_D0_MARK, MMC_D1_MARK,
1116 MMC_D2_MARK, MMC_D3_MARK,
1117 MMC_D4_MARK, MMC_D5_MARK,
1118 MMC_D6_MARK, MMC_D7_MARK,
1119 };
1120 static const unsigned int mmc_ctrl_pins[] = {
1121 /* CLK, CMD */
1122 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1123 };
1124 static const unsigned int mmc_ctrl_mux[] = {
1125 MMC_CLK_MARK, MMC_CMD_MARK,
1126 };
1127 static const unsigned int mmc_cd_pins[] = {
1128 /* CD */
1129 RCAR_GP_PIN(3, 16),
1130 };
1131 static const unsigned int mmc_cd_mux[] = {
1132 MMC_CD_MARK,
1133 };
1134 static const unsigned int mmc_wp_pins[] = {
1135 /* WP */
1136 RCAR_GP_PIN(3, 15),
1137 };
1138 static const unsigned int mmc_wp_mux[] = {
1139 MMC_WP_MARK,
1140 };
1141
1142 /* - MSIOF0 ----------------------------------------------------------------- */
1143 static const unsigned int msiof0_clk_pins[] = {
1144 /* SCK */
1145 RCAR_GP_PIN(4, 2),
1146 };
1147 static const unsigned int msiof0_clk_mux[] = {
1148 MSIOF0_SCK_MARK,
1149 };
1150 static const unsigned int msiof0_sync_pins[] = {
1151 /* SYNC */
1152 RCAR_GP_PIN(4, 3),
1153 };
1154 static const unsigned int msiof0_sync_mux[] = {
1155 MSIOF0_SYNC_MARK,
1156 };
1157 static const unsigned int msiof0_ss1_pins[] = {
1158 /* SS1 */
1159 RCAR_GP_PIN(4, 4),
1160 };
1161 static const unsigned int msiof0_ss1_mux[] = {
1162 MSIOF0_SS1_MARK,
1163 };
1164 static const unsigned int msiof0_ss2_pins[] = {
1165 /* SS2 */
1166 RCAR_GP_PIN(4, 5),
1167 };
1168 static const unsigned int msiof0_ss2_mux[] = {
1169 MSIOF0_SS2_MARK,
1170 };
1171 static const unsigned int msiof0_txd_pins[] = {
1172 /* TXD */
1173 RCAR_GP_PIN(4, 1),
1174 };
1175 static const unsigned int msiof0_txd_mux[] = {
1176 MSIOF0_TXD_MARK,
1177 };
1178 static const unsigned int msiof0_rxd_pins[] = {
1179 /* RXD */
1180 RCAR_GP_PIN(4, 0),
1181 };
1182 static const unsigned int msiof0_rxd_mux[] = {
1183 MSIOF0_RXD_MARK,
1184 };
1185
1186 /* - MSIOF1 ----------------------------------------------------------------- */
1187 static const unsigned int msiof1_clk_pins[] = {
1188 /* SCK */
1189 RCAR_GP_PIN(3, 2),
1190 };
1191 static const unsigned int msiof1_clk_mux[] = {
1192 MSIOF1_SCK_MARK,
1193 };
1194 static const unsigned int msiof1_sync_pins[] = {
1195 /* SYNC */
1196 RCAR_GP_PIN(3, 3),
1197 };
1198 static const unsigned int msiof1_sync_mux[] = {
1199 MSIOF1_SYNC_MARK,
1200 };
1201 static const unsigned int msiof1_ss1_pins[] = {
1202 /* SS1 */
1203 RCAR_GP_PIN(3, 4),
1204 };
1205 static const unsigned int msiof1_ss1_mux[] = {
1206 MSIOF1_SS1_MARK,
1207 };
1208 static const unsigned int msiof1_ss2_pins[] = {
1209 /* SS2 */
1210 RCAR_GP_PIN(3, 5),
1211 };
1212 static const unsigned int msiof1_ss2_mux[] = {
1213 MSIOF1_SS2_MARK,
1214 };
1215 static const unsigned int msiof1_txd_pins[] = {
1216 /* TXD */
1217 RCAR_GP_PIN(3, 1),
1218 };
1219 static const unsigned int msiof1_txd_mux[] = {
1220 MSIOF1_TXD_MARK,
1221 };
1222 static const unsigned int msiof1_rxd_pins[] = {
1223 /* RXD */
1224 RCAR_GP_PIN(3, 0),
1225 };
1226 static const unsigned int msiof1_rxd_mux[] = {
1227 MSIOF1_RXD_MARK,
1228 };
1229
1230 /* - MSIOF2 ----------------------------------------------------------------- */
1231 static const unsigned int msiof2_clk_pins[] = {
1232 /* SCK */
1233 RCAR_GP_PIN(2, 0),
1234 };
1235 static const unsigned int msiof2_clk_mux[] = {
1236 MSIOF2_SCK_MARK,
1237 };
1238 static const unsigned int msiof2_sync_pins[] = {
1239 /* SYNC */
1240 RCAR_GP_PIN(2, 3),
1241 };
1242 static const unsigned int msiof2_sync_mux[] = {
1243 MSIOF2_SYNC_MARK,
1244 };
1245 static const unsigned int msiof2_ss1_pins[] = {
1246 /* SS1 */
1247 RCAR_GP_PIN(2, 4),
1248 };
1249 static const unsigned int msiof2_ss1_mux[] = {
1250 MSIOF2_SS1_MARK,
1251 };
1252 static const unsigned int msiof2_ss2_pins[] = {
1253 /* SS2 */
1254 RCAR_GP_PIN(2, 5),
1255 };
1256 static const unsigned int msiof2_ss2_mux[] = {
1257 MSIOF2_SS2_MARK,
1258 };
1259 static const unsigned int msiof2_txd_pins[] = {
1260 /* TXD */
1261 RCAR_GP_PIN(2, 2),
1262 };
1263 static const unsigned int msiof2_txd_mux[] = {
1264 MSIOF2_TXD_MARK,
1265 };
1266 static const unsigned int msiof2_rxd_pins[] = {
1267 /* RXD */
1268 RCAR_GP_PIN(2, 1),
1269 };
1270 static const unsigned int msiof2_rxd_mux[] = {
1271 MSIOF2_RXD_MARK,
1272 };
1273
1274 /* - MSIOF3 ----------------------------------------------------------------- */
1275 static const unsigned int msiof3_clk_pins[] = {
1276 /* SCK */
1277 RCAR_GP_PIN(0, 20),
1278 };
1279 static const unsigned int msiof3_clk_mux[] = {
1280 MSIOF3_SCK_MARK,
1281 };
1282 static const unsigned int msiof3_sync_pins[] = {
1283 /* SYNC */
1284 RCAR_GP_PIN(0, 21),
1285 };
1286 static const unsigned int msiof3_sync_mux[] = {
1287 MSIOF3_SYNC_MARK,
1288 };
1289 static const unsigned int msiof3_ss1_pins[] = {
1290 /* SS1 */
1291 RCAR_GP_PIN(0, 6),
1292 };
1293 static const unsigned int msiof3_ss1_mux[] = {
1294 MSIOF3_SS1_MARK,
1295 };
1296 static const unsigned int msiof3_ss2_pins[] = {
1297 /* SS2 */
1298 RCAR_GP_PIN(0, 7),
1299 };
1300 static const unsigned int msiof3_ss2_mux[] = {
1301 MSIOF3_SS2_MARK,
1302 };
1303 static const unsigned int msiof3_txd_pins[] = {
1304 /* TXD */
1305 RCAR_GP_PIN(0, 5),
1306 };
1307 static const unsigned int msiof3_txd_mux[] = {
1308 MSIOF3_TXD_MARK,
1309 };
1310 static const unsigned int msiof3_rxd_pins[] = {
1311 /* RXD */
1312 RCAR_GP_PIN(0, 4),
1313 };
1314 static const unsigned int msiof3_rxd_mux[] = {
1315 MSIOF3_RXD_MARK,
1316 };
1317
1318 /* - PWM0 ------------------------------------------------------------------- */
1319 static const unsigned int pwm0_a_pins[] = {
1320 RCAR_GP_PIN(2, 12),
1321 };
1322 static const unsigned int pwm0_a_mux[] = {
1323 PWM0_A_MARK,
1324 };
1325 static const unsigned int pwm0_b_pins[] = {
1326 RCAR_GP_PIN(1, 21),
1327 };
1328 static const unsigned int pwm0_b_mux[] = {
1329 PWM0_B_MARK,
1330 };
1331
1332 /* - PWM1 ------------------------------------------------------------------- */
1333 static const unsigned int pwm1_a_pins[] = {
1334 RCAR_GP_PIN(2, 13),
1335 };
1336 static const unsigned int pwm1_a_mux[] = {
1337 PWM1_A_MARK,
1338 };
1339 static const unsigned int pwm1_b_pins[] = {
1340 RCAR_GP_PIN(1, 22),
1341 };
1342 static const unsigned int pwm1_b_mux[] = {
1343 PWM1_B_MARK,
1344 };
1345
1346 /* - PWM2 ------------------------------------------------------------------- */
1347 static const unsigned int pwm2_a_pins[] = {
1348 RCAR_GP_PIN(2, 14),
1349 };
1350 static const unsigned int pwm2_a_mux[] = {
1351 PWM2_A_MARK,
1352 };
1353 static const unsigned int pwm2_b_pins[] = {
1354 RCAR_GP_PIN(1, 23),
1355 };
1356 static const unsigned int pwm2_b_mux[] = {
1357 PWM2_B_MARK,
1358 };
1359
1360 /* - PWM3 ------------------------------------------------------------------- */
1361 static const unsigned int pwm3_a_pins[] = {
1362 RCAR_GP_PIN(2, 15),
1363 };
1364 static const unsigned int pwm3_a_mux[] = {
1365 PWM3_A_MARK,
1366 };
1367 static const unsigned int pwm3_b_pins[] = {
1368 RCAR_GP_PIN(1, 24),
1369 };
1370 static const unsigned int pwm3_b_mux[] = {
1371 PWM3_B_MARK,
1372 };
1373
1374 /* - PWM4 ------------------------------------------------------------------- */
1375 static const unsigned int pwm4_a_pins[] = {
1376 RCAR_GP_PIN(2, 16),
1377 };
1378 static const unsigned int pwm4_a_mux[] = {
1379 PWM4_A_MARK,
1380 };
1381 static const unsigned int pwm4_b_pins[] = {
1382 RCAR_GP_PIN(1, 25),
1383 };
1384 static const unsigned int pwm4_b_mux[] = {
1385 PWM4_B_MARK,
1386 };
1387
1388 /* - SCIF Clock ------------------------------------------------------------- */
1389 static const unsigned int scif_clk_a_pins[] = {
1390 /* SCIF_CLK */
1391 RCAR_GP_PIN(0, 18),
1392 };
1393 static const unsigned int scif_clk_a_mux[] = {
1394 SCIF_CLK_A_MARK,
1395 };
1396 static const unsigned int scif_clk_b_pins[] = {
1397 /* SCIF_CLK */
1398 RCAR_GP_PIN(1, 25),
1399 };
1400 static const unsigned int scif_clk_b_mux[] = {
1401 SCIF_CLK_B_MARK,
1402 };
1403
1404 /* - SCIF0 ------------------------------------------------------------------ */
1405 static const unsigned int scif0_data_pins[] = {
1406 /* RX, TX */
1407 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1408 };
1409 static const unsigned int scif0_data_mux[] = {
1410 RX0_MARK, TX0_MARK,
1411 };
1412 static const unsigned int scif0_clk_pins[] = {
1413 /* SCK */
1414 RCAR_GP_PIN(4, 1),
1415 };
1416 static const unsigned int scif0_clk_mux[] = {
1417 SCK0_MARK,
1418 };
1419 static const unsigned int scif0_ctrl_pins[] = {
1420 /* RTS#, CTS# */
1421 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1422 };
1423 static const unsigned int scif0_ctrl_mux[] = {
1424 RTS0_N_TANS_MARK, CTS0_N_MARK,
1425 };
1426
1427 /* - SCIF1 ------------------------------------------------------------------ */
1428 static const unsigned int scif1_data_a_pins[] = {
1429 /* RX, TX */
1430 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1431 };
1432 static const unsigned int scif1_data_a_mux[] = {
1433 RX1_A_MARK, TX1_A_MARK,
1434 };
1435 static const unsigned int scif1_clk_pins[] = {
1436 /* SCK */
1437 RCAR_GP_PIN(2, 5),
1438 };
1439 static const unsigned int scif1_clk_mux[] = {
1440 SCK1_MARK,
1441 };
1442 static const unsigned int scif1_ctrl_pins[] = {
1443 /* RTS#, CTS# */
1444 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1445 };
1446 static const unsigned int scif1_ctrl_mux[] = {
1447 RTS1_N_TANS_MARK, CTS1_N_MARK,
1448 };
1449 static const unsigned int scif1_data_b_pins[] = {
1450 /* RX, TX */
1451 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1452 };
1453 static const unsigned int scif1_data_b_mux[] = {
1454 RX1_B_MARK, TX1_B_MARK,
1455 };
1456
1457 /* - SCIF3 ------------------------------------------------------------------ */
1458 static const unsigned int scif3_data_pins[] = {
1459 /* RX, TX */
1460 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1461 };
1462 static const unsigned int scif3_data_mux[] = {
1463 RX3_MARK, TX3_MARK,
1464 };
1465 static const unsigned int scif3_clk_pins[] = {
1466 /* SCK */
1467 RCAR_GP_PIN(2, 0),
1468 };
1469 static const unsigned int scif3_clk_mux[] = {
1470 SCK3_MARK,
1471 };
1472 static const unsigned int scif3_ctrl_pins[] = {
1473 /* RTS#, CTS# */
1474 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1475 };
1476 static const unsigned int scif3_ctrl_mux[] = {
1477 RTS3_N_TANS_MARK, CTS3_N_MARK,
1478 };
1479
1480 /* - SCIF4 ------------------------------------------------------------------ */
1481 static const unsigned int scif4_data_pins[] = {
1482 /* RX, TX */
1483 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1484 };
1485 static const unsigned int scif4_data_mux[] = {
1486 RX4_MARK, TX4_MARK,
1487 };
1488 static const unsigned int scif4_clk_pins[] = {
1489 /* SCK */
1490 RCAR_GP_PIN(3, 9),
1491 };
1492 static const unsigned int scif4_clk_mux[] = {
1493 SCK4_MARK,
1494 };
1495 static const unsigned int scif4_ctrl_pins[] = {
1496 /* RTS#, CTS# */
1497 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1498 };
1499 static const unsigned int scif4_ctrl_mux[] = {
1500 RTS4_N_TANS_MARK, CTS4_N_MARK,
1501 };
1502
1503 /* - TMU -------------------------------------------------------------------- */
1504 static const unsigned int tmu_tclk1_a_pins[] = {
1505 /* TCLK1 */
1506 RCAR_GP_PIN(4, 4),
1507 };
1508 static const unsigned int tmu_tclk1_a_mux[] = {
1509 TCLK1_A_MARK,
1510 };
1511 static const unsigned int tmu_tclk1_b_pins[] = {
1512 /* TCLK1 */
1513 RCAR_GP_PIN(1, 23),
1514 };
1515 static const unsigned int tmu_tclk1_b_mux[] = {
1516 TCLK1_B_MARK,
1517 };
1518 static const unsigned int tmu_tclk2_a_pins[] = {
1519 /* TCLK2 */
1520 RCAR_GP_PIN(4, 5),
1521 };
1522 static const unsigned int tmu_tclk2_a_mux[] = {
1523 TCLK2_A_MARK,
1524 };
1525 static const unsigned int tmu_tclk2_b_pins[] = {
1526 /* TCLK2 */
1527 RCAR_GP_PIN(1, 24),
1528 };
1529 static const unsigned int tmu_tclk2_b_mux[] = {
1530 TCLK2_B_MARK,
1531 };
1532
1533 /* - VIN0 ------------------------------------------------------------------- */
1534 static const unsigned int vin0_data8_pins[] = {
1535 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1536 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1537 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1538 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1539 };
1540 static const unsigned int vin0_data8_mux[] = {
1541 VI0_DATA0_MARK, VI0_DATA1_MARK,
1542 VI0_DATA2_MARK, VI0_DATA3_MARK,
1543 VI0_DATA4_MARK, VI0_DATA5_MARK,
1544 VI0_DATA6_MARK, VI0_DATA7_MARK,
1545 };
1546 static const unsigned int vin0_data10_pins[] = {
1547 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1548 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1549 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1550 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1551 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1552 };
1553 static const unsigned int vin0_data10_mux[] = {
1554 VI0_DATA0_MARK, VI0_DATA1_MARK,
1555 VI0_DATA2_MARK, VI0_DATA3_MARK,
1556 VI0_DATA4_MARK, VI0_DATA5_MARK,
1557 VI0_DATA6_MARK, VI0_DATA7_MARK,
1558 VI0_DATA8_MARK, VI0_DATA9_MARK,
1559 };
1560 static const unsigned int vin0_data12_pins[] = {
1561 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1562 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1563 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1564 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1565 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1566 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1567 };
1568 static const unsigned int vin0_data12_mux[] = {
1569 VI0_DATA0_MARK, VI0_DATA1_MARK,
1570 VI0_DATA2_MARK, VI0_DATA3_MARK,
1571 VI0_DATA4_MARK, VI0_DATA5_MARK,
1572 VI0_DATA6_MARK, VI0_DATA7_MARK,
1573 VI0_DATA8_MARK, VI0_DATA9_MARK,
1574 VI0_DATA10_MARK, VI0_DATA11_MARK,
1575 };
1576 static const unsigned int vin0_sync_pins[] = {
1577 /* HSYNC#, VSYNC# */
1578 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1579 };
1580 static const unsigned int vin0_sync_mux[] = {
1581 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1582 };
1583 static const unsigned int vin0_field_pins[] = {
1584 /* FIELD */
1585 RCAR_GP_PIN(2, 16),
1586 };
1587 static const unsigned int vin0_field_mux[] = {
1588 VI0_FIELD_MARK,
1589 };
1590 static const unsigned int vin0_clkenb_pins[] = {
1591 /* CLKENB */
1592 RCAR_GP_PIN(2, 1),
1593 };
1594 static const unsigned int vin0_clkenb_mux[] = {
1595 VI0_CLKENB_MARK,
1596 };
1597 static const unsigned int vin0_clk_pins[] = {
1598 /* CLK */
1599 RCAR_GP_PIN(2, 0),
1600 };
1601 static const unsigned int vin0_clk_mux[] = {
1602 VI0_CLK_MARK,
1603 };
1604
1605 /* - VIN1 ------------------------------------------------------------------- */
1606 static const unsigned int vin1_data8_pins[] = {
1607 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1608 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1609 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1610 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1611 };
1612 static const unsigned int vin1_data8_mux[] = {
1613 VI1_DATA0_MARK, VI1_DATA1_MARK,
1614 VI1_DATA2_MARK, VI1_DATA3_MARK,
1615 VI1_DATA4_MARK, VI1_DATA5_MARK,
1616 VI1_DATA6_MARK, VI1_DATA7_MARK,
1617 };
1618 static const unsigned int vin1_data10_pins[] = {
1619 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1620 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1621 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1622 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1623 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1624 };
1625 static const unsigned int vin1_data10_mux[] = {
1626 VI1_DATA0_MARK, VI1_DATA1_MARK,
1627 VI1_DATA2_MARK, VI1_DATA3_MARK,
1628 VI1_DATA4_MARK, VI1_DATA5_MARK,
1629 VI1_DATA6_MARK, VI1_DATA7_MARK,
1630 VI1_DATA8_MARK, VI1_DATA9_MARK,
1631 };
1632 static const unsigned int vin1_data12_pins[] = {
1633 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1634 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1635 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1636 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1637 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1638 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1639 };
1640 static const unsigned int vin1_data12_mux[] = {
1641 VI1_DATA0_MARK, VI1_DATA1_MARK,
1642 VI1_DATA2_MARK, VI1_DATA3_MARK,
1643 VI1_DATA4_MARK, VI1_DATA5_MARK,
1644 VI1_DATA6_MARK, VI1_DATA7_MARK,
1645 VI1_DATA8_MARK, VI1_DATA9_MARK,
1646 VI1_DATA10_MARK, VI1_DATA11_MARK,
1647 };
1648 static const unsigned int vin1_sync_pins[] = {
1649 /* HSYNC#, VSYNC# */
1650 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1651 };
1652 static const unsigned int vin1_sync_mux[] = {
1653 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1654 };
1655 static const unsigned int vin1_field_pins[] = {
1656 RCAR_GP_PIN(3, 16),
1657 };
1658 static const unsigned int vin1_field_mux[] = {
1659 /* FIELD */
1660 VI1_FIELD_MARK,
1661 };
1662 static const unsigned int vin1_clkenb_pins[] = {
1663 RCAR_GP_PIN(3, 1),
1664 };
1665 static const unsigned int vin1_clkenb_mux[] = {
1666 /* CLKENB */
1667 VI1_CLKENB_MARK,
1668 };
1669 static const unsigned int vin1_clk_pins[] = {
1670 RCAR_GP_PIN(3, 0),
1671 };
1672 static const unsigned int vin1_clk_mux[] = {
1673 /* CLK */
1674 VI1_CLK_MARK,
1675 };
1676
1677 static const struct sh_pfc_pin_group pinmux_groups[] = {
1678 SH_PFC_PIN_GROUP(avb0_link),
1679 SH_PFC_PIN_GROUP(avb0_magic),
1680 SH_PFC_PIN_GROUP(avb0_phy_int),
1681 SH_PFC_PIN_GROUP(avb0_mdio),
1682 SH_PFC_PIN_GROUP(avb0_rgmii),
1683 SH_PFC_PIN_GROUP(avb0_txcrefclk),
1684 SH_PFC_PIN_GROUP(avb0_avtp_pps),
1685 SH_PFC_PIN_GROUP(avb0_avtp_capture),
1686 SH_PFC_PIN_GROUP(avb0_avtp_match),
1687 SH_PFC_PIN_GROUP(canfd_clk_a),
1688 SH_PFC_PIN_GROUP(canfd_clk_b),
1689 SH_PFC_PIN_GROUP(canfd0_data_a),
1690 SH_PFC_PIN_GROUP(canfd0_data_b),
1691 SH_PFC_PIN_GROUP(canfd1_data),
1692 SH_PFC_PIN_GROUP(du_rgb666),
1693 SH_PFC_PIN_GROUP(du_clk_out),
1694 SH_PFC_PIN_GROUP(du_sync),
1695 SH_PFC_PIN_GROUP(du_oddf),
1696 SH_PFC_PIN_GROUP(du_cde),
1697 SH_PFC_PIN_GROUP(du_disp),
1698 SH_PFC_PIN_GROUP(hscif0_data),
1699 SH_PFC_PIN_GROUP(hscif0_clk),
1700 SH_PFC_PIN_GROUP(hscif0_ctrl),
1701 SH_PFC_PIN_GROUP(hscif1_data),
1702 SH_PFC_PIN_GROUP(hscif1_clk),
1703 SH_PFC_PIN_GROUP(hscif1_ctrl),
1704 SH_PFC_PIN_GROUP(hscif2_data),
1705 SH_PFC_PIN_GROUP(hscif2_clk),
1706 SH_PFC_PIN_GROUP(hscif2_ctrl),
1707 SH_PFC_PIN_GROUP(hscif3_data),
1708 SH_PFC_PIN_GROUP(hscif3_clk),
1709 SH_PFC_PIN_GROUP(hscif3_ctrl),
1710 SH_PFC_PIN_GROUP(i2c0),
1711 SH_PFC_PIN_GROUP(i2c1),
1712 SH_PFC_PIN_GROUP(i2c2),
1713 SH_PFC_PIN_GROUP(i2c3_a),
1714 SH_PFC_PIN_GROUP(i2c3_b),
1715 SH_PFC_PIN_GROUP(i2c4),
1716 SH_PFC_PIN_GROUP(intc_ex_irq0),
1717 SH_PFC_PIN_GROUP(intc_ex_irq1),
1718 SH_PFC_PIN_GROUP(intc_ex_irq2),
1719 SH_PFC_PIN_GROUP(intc_ex_irq3),
1720 SH_PFC_PIN_GROUP(intc_ex_irq4),
1721 SH_PFC_PIN_GROUP(intc_ex_irq5),
1722 SH_PFC_PIN_GROUP(mmc_data1),
1723 SH_PFC_PIN_GROUP(mmc_data4),
1724 SH_PFC_PIN_GROUP(mmc_data8),
1725 SH_PFC_PIN_GROUP(mmc_ctrl),
1726 SH_PFC_PIN_GROUP(mmc_cd),
1727 SH_PFC_PIN_GROUP(mmc_wp),
1728 SH_PFC_PIN_GROUP(msiof0_clk),
1729 SH_PFC_PIN_GROUP(msiof0_sync),
1730 SH_PFC_PIN_GROUP(msiof0_ss1),
1731 SH_PFC_PIN_GROUP(msiof0_ss2),
1732 SH_PFC_PIN_GROUP(msiof0_txd),
1733 SH_PFC_PIN_GROUP(msiof0_rxd),
1734 SH_PFC_PIN_GROUP(msiof1_clk),
1735 SH_PFC_PIN_GROUP(msiof1_sync),
1736 SH_PFC_PIN_GROUP(msiof1_ss1),
1737 SH_PFC_PIN_GROUP(msiof1_ss2),
1738 SH_PFC_PIN_GROUP(msiof1_txd),
1739 SH_PFC_PIN_GROUP(msiof1_rxd),
1740 SH_PFC_PIN_GROUP(msiof2_clk),
1741 SH_PFC_PIN_GROUP(msiof2_sync),
1742 SH_PFC_PIN_GROUP(msiof2_ss1),
1743 SH_PFC_PIN_GROUP(msiof2_ss2),
1744 SH_PFC_PIN_GROUP(msiof2_txd),
1745 SH_PFC_PIN_GROUP(msiof2_rxd),
1746 SH_PFC_PIN_GROUP(msiof3_clk),
1747 SH_PFC_PIN_GROUP(msiof3_sync),
1748 SH_PFC_PIN_GROUP(msiof3_ss1),
1749 SH_PFC_PIN_GROUP(msiof3_ss2),
1750 SH_PFC_PIN_GROUP(msiof3_txd),
1751 SH_PFC_PIN_GROUP(msiof3_rxd),
1752 SH_PFC_PIN_GROUP(pwm0_a),
1753 SH_PFC_PIN_GROUP(pwm0_b),
1754 SH_PFC_PIN_GROUP(pwm1_a),
1755 SH_PFC_PIN_GROUP(pwm1_b),
1756 SH_PFC_PIN_GROUP(pwm2_a),
1757 SH_PFC_PIN_GROUP(pwm2_b),
1758 SH_PFC_PIN_GROUP(pwm3_a),
1759 SH_PFC_PIN_GROUP(pwm3_b),
1760 SH_PFC_PIN_GROUP(pwm4_a),
1761 SH_PFC_PIN_GROUP(pwm4_b),
1762 SH_PFC_PIN_GROUP(scif_clk_a),
1763 SH_PFC_PIN_GROUP(scif_clk_b),
1764 SH_PFC_PIN_GROUP(scif0_data),
1765 SH_PFC_PIN_GROUP(scif0_clk),
1766 SH_PFC_PIN_GROUP(scif0_ctrl),
1767 SH_PFC_PIN_GROUP(scif1_data_a),
1768 SH_PFC_PIN_GROUP(scif1_clk),
1769 SH_PFC_PIN_GROUP(scif1_ctrl),
1770 SH_PFC_PIN_GROUP(scif1_data_b),
1771 SH_PFC_PIN_GROUP(scif3_data),
1772 SH_PFC_PIN_GROUP(scif3_clk),
1773 SH_PFC_PIN_GROUP(scif3_ctrl),
1774 SH_PFC_PIN_GROUP(scif4_data),
1775 SH_PFC_PIN_GROUP(scif4_clk),
1776 SH_PFC_PIN_GROUP(scif4_ctrl),
1777 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1778 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1779 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1780 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1781 SH_PFC_PIN_GROUP(vin0_data8),
1782 SH_PFC_PIN_GROUP(vin0_data10),
1783 SH_PFC_PIN_GROUP(vin0_data12),
1784 SH_PFC_PIN_GROUP(vin0_sync),
1785 SH_PFC_PIN_GROUP(vin0_field),
1786 SH_PFC_PIN_GROUP(vin0_clkenb),
1787 SH_PFC_PIN_GROUP(vin0_clk),
1788 SH_PFC_PIN_GROUP(vin1_data8),
1789 SH_PFC_PIN_GROUP(vin1_data10),
1790 SH_PFC_PIN_GROUP(vin1_data12),
1791 SH_PFC_PIN_GROUP(vin1_sync),
1792 SH_PFC_PIN_GROUP(vin1_field),
1793 SH_PFC_PIN_GROUP(vin1_clkenb),
1794 SH_PFC_PIN_GROUP(vin1_clk),
1795 };
1796
1797 static const char * const avb0_groups[] = {
1798 "avb0_link",
1799 "avb0_magic",
1800 "avb0_phy_int",
1801 "avb0_mdio",
1802 "avb0_rgmii",
1803 "avb0_txcrefclk",
1804 "avb0_avtp_pps",
1805 "avb0_avtp_capture",
1806 "avb0_avtp_match",
1807 };
1808
1809 static const char * const canfd_clk_groups[] = {
1810 "canfd_clk_a",
1811 "canfd_clk_b",
1812 };
1813
1814 static const char * const canfd0_groups[] = {
1815 "canfd0_data_a",
1816 "canfd0_data_b",
1817 };
1818
1819 static const char * const canfd1_groups[] = {
1820 "canfd1_data",
1821 };
1822
1823 static const char * const du_groups[] = {
1824 "du_rgb666",
1825 "du_clk_out",
1826 "du_sync",
1827 "du_oddf",
1828 "du_cde",
1829 "du_disp",
1830 };
1831
1832 static const char * const hscif0_groups[] = {
1833 "hscif0_data",
1834 "hscif0_clk",
1835 "hscif0_ctrl",
1836 };
1837
1838 static const char * const hscif1_groups[] = {
1839 "hscif1_data",
1840 "hscif1_clk",
1841 "hscif1_ctrl",
1842 };
1843
1844 static const char * const hscif2_groups[] = {
1845 "hscif2_data",
1846 "hscif2_clk",
1847 "hscif2_ctrl",
1848 };
1849
1850 static const char * const hscif3_groups[] = {
1851 "hscif3_data",
1852 "hscif3_clk",
1853 "hscif3_ctrl",
1854 };
1855
1856 static const char * const i2c0_groups[] = {
1857 "i2c0",
1858 };
1859
1860 static const char * const i2c1_groups[] = {
1861 "i2c1",
1862 };
1863
1864 static const char * const i2c2_groups[] = {
1865 "i2c2",
1866 };
1867
1868 static const char * const i2c3_groups[] = {
1869 "i2c3_a",
1870 "i2c3_b",
1871 };
1872
1873 static const char * const i2c4_groups[] = {
1874 "i2c4",
1875 };
1876
1877 static const char * const intc_ex_groups[] = {
1878 "intc_ex_irq0",
1879 "intc_ex_irq1",
1880 "intc_ex_irq2",
1881 "intc_ex_irq3",
1882 "intc_ex_irq4",
1883 "intc_ex_irq5",
1884 };
1885
1886 static const char * const mmc_groups[] = {
1887 "mmc_data1",
1888 "mmc_data4",
1889 "mmc_data8",
1890 "mmc_ctrl",
1891 "mmc_cd",
1892 "mmc_wp",
1893 };
1894
1895 static const char * const msiof0_groups[] = {
1896 "msiof0_clk",
1897 "msiof0_sync",
1898 "msiof0_ss1",
1899 "msiof0_ss2",
1900 "msiof0_txd",
1901 "msiof0_rxd",
1902 };
1903
1904 static const char * const msiof1_groups[] = {
1905 "msiof1_clk",
1906 "msiof1_sync",
1907 "msiof1_ss1",
1908 "msiof1_ss2",
1909 "msiof1_txd",
1910 "msiof1_rxd",
1911 };
1912
1913 static const char * const msiof2_groups[] = {
1914 "msiof2_clk",
1915 "msiof2_sync",
1916 "msiof2_ss1",
1917 "msiof2_ss2",
1918 "msiof2_txd",
1919 "msiof2_rxd",
1920 };
1921
1922 static const char * const msiof3_groups[] = {
1923 "msiof3_clk",
1924 "msiof3_sync",
1925 "msiof3_ss1",
1926 "msiof3_ss2",
1927 "msiof3_txd",
1928 "msiof3_rxd",
1929 };
1930
1931 static const char * const pwm0_groups[] = {
1932 "pwm0_a",
1933 "pwm0_b",
1934 };
1935
1936 static const char * const pwm1_groups[] = {
1937 "pwm1_a",
1938 "pwm1_b",
1939 };
1940
1941 static const char * const pwm2_groups[] = {
1942 "pwm2_a",
1943 "pwm2_b",
1944 };
1945
1946 static const char * const pwm3_groups[] = {
1947 "pwm3_a",
1948 "pwm3_b",
1949 };
1950
1951 static const char * const pwm4_groups[] = {
1952 "pwm4_a",
1953 "pwm4_b",
1954 };
1955
1956 static const char * const scif_clk_groups[] = {
1957 "scif_clk_a",
1958 "scif_clk_b",
1959 };
1960
1961 static const char * const scif0_groups[] = {
1962 "scif0_data",
1963 "scif0_clk",
1964 "scif0_ctrl",
1965 };
1966
1967 static const char * const scif1_groups[] = {
1968 "scif1_data_a",
1969 "scif1_clk",
1970 "scif1_ctrl",
1971 "scif1_data_b",
1972 };
1973
1974 static const char * const scif3_groups[] = {
1975 "scif3_data",
1976 "scif3_clk",
1977 "scif3_ctrl",
1978 };
1979
1980 static const char * const scif4_groups[] = {
1981 "scif4_data",
1982 "scif4_clk",
1983 "scif4_ctrl",
1984 };
1985
1986 static const char * const tmu_groups[] = {
1987 "tmu_tclk1_a",
1988 "tmu_tclk1_b",
1989 "tmu_tclk2_a",
1990 "tmu_tclk2_b",
1991 };
1992
1993 static const char * const vin0_groups[] = {
1994 "vin0_data8",
1995 "vin0_data10",
1996 "vin0_data12",
1997 "vin0_sync",
1998 "vin0_field",
1999 "vin0_clkenb",
2000 "vin0_clk",
2001 };
2002
2003 static const char * const vin1_groups[] = {
2004 "vin1_data8",
2005 "vin1_data10",
2006 "vin1_data12",
2007 "vin1_sync",
2008 "vin1_field",
2009 "vin1_clkenb",
2010 "vin1_clk",
2011 };
2012
2013 static const struct sh_pfc_function pinmux_functions[] = {
2014 SH_PFC_FUNCTION(avb0),
2015 SH_PFC_FUNCTION(canfd_clk),
2016 SH_PFC_FUNCTION(canfd0),
2017 SH_PFC_FUNCTION(canfd1),
2018 SH_PFC_FUNCTION(du),
2019 SH_PFC_FUNCTION(hscif0),
2020 SH_PFC_FUNCTION(hscif1),
2021 SH_PFC_FUNCTION(hscif2),
2022 SH_PFC_FUNCTION(hscif3),
2023 SH_PFC_FUNCTION(i2c0),
2024 SH_PFC_FUNCTION(i2c1),
2025 SH_PFC_FUNCTION(i2c2),
2026 SH_PFC_FUNCTION(i2c3),
2027 SH_PFC_FUNCTION(i2c4),
2028 SH_PFC_FUNCTION(intc_ex),
2029 SH_PFC_FUNCTION(mmc),
2030 SH_PFC_FUNCTION(msiof0),
2031 SH_PFC_FUNCTION(msiof1),
2032 SH_PFC_FUNCTION(msiof2),
2033 SH_PFC_FUNCTION(msiof3),
2034 SH_PFC_FUNCTION(pwm0),
2035 SH_PFC_FUNCTION(pwm1),
2036 SH_PFC_FUNCTION(pwm2),
2037 SH_PFC_FUNCTION(pwm3),
2038 SH_PFC_FUNCTION(pwm4),
2039 SH_PFC_FUNCTION(scif_clk),
2040 SH_PFC_FUNCTION(scif0),
2041 SH_PFC_FUNCTION(scif1),
2042 SH_PFC_FUNCTION(scif3),
2043 SH_PFC_FUNCTION(scif4),
2044 SH_PFC_FUNCTION(tmu),
2045 SH_PFC_FUNCTION(vin0),
2046 SH_PFC_FUNCTION(vin1),
2047 };
2048
2049 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2050 #define F_(x, y) FN_##y
2051 #define FM(x) FN_##x
2052 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2053 0, 0,
2054 0, 0,
2055 0, 0,
2056 0, 0,
2057 0, 0,
2058 0, 0,
2059 0, 0,
2060 0, 0,
2061 0, 0,
2062 0, 0,
2063 GP_0_21_FN, GPSR0_21,
2064 GP_0_20_FN, GPSR0_20,
2065 GP_0_19_FN, GPSR0_19,
2066 GP_0_18_FN, GPSR0_18,
2067 GP_0_17_FN, GPSR0_17,
2068 GP_0_16_FN, GPSR0_16,
2069 GP_0_15_FN, GPSR0_15,
2070 GP_0_14_FN, GPSR0_14,
2071 GP_0_13_FN, GPSR0_13,
2072 GP_0_12_FN, GPSR0_12,
2073 GP_0_11_FN, GPSR0_11,
2074 GP_0_10_FN, GPSR0_10,
2075 GP_0_9_FN, GPSR0_9,
2076 GP_0_8_FN, GPSR0_8,
2077 GP_0_7_FN, GPSR0_7,
2078 GP_0_6_FN, GPSR0_6,
2079 GP_0_5_FN, GPSR0_5,
2080 GP_0_4_FN, GPSR0_4,
2081 GP_0_3_FN, GPSR0_3,
2082 GP_0_2_FN, GPSR0_2,
2083 GP_0_1_FN, GPSR0_1,
2084 GP_0_0_FN, GPSR0_0, }
2085 },
2086 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2087 0, 0,
2088 0, 0,
2089 0, 0,
2090 0, 0,
2091 GP_1_27_FN, GPSR1_27,
2092 GP_1_26_FN, GPSR1_26,
2093 GP_1_25_FN, GPSR1_25,
2094 GP_1_24_FN, GPSR1_24,
2095 GP_1_23_FN, GPSR1_23,
2096 GP_1_22_FN, GPSR1_22,
2097 GP_1_21_FN, GPSR1_21,
2098 GP_1_20_FN, GPSR1_20,
2099 GP_1_19_FN, GPSR1_19,
2100 GP_1_18_FN, GPSR1_18,
2101 GP_1_17_FN, GPSR1_17,
2102 GP_1_16_FN, GPSR1_16,
2103 GP_1_15_FN, GPSR1_15,
2104 GP_1_14_FN, GPSR1_14,
2105 GP_1_13_FN, GPSR1_13,
2106 GP_1_12_FN, GPSR1_12,
2107 GP_1_11_FN, GPSR1_11,
2108 GP_1_10_FN, GPSR1_10,
2109 GP_1_9_FN, GPSR1_9,
2110 GP_1_8_FN, GPSR1_8,
2111 GP_1_7_FN, GPSR1_7,
2112 GP_1_6_FN, GPSR1_6,
2113 GP_1_5_FN, GPSR1_5,
2114 GP_1_4_FN, GPSR1_4,
2115 GP_1_3_FN, GPSR1_3,
2116 GP_1_2_FN, GPSR1_2,
2117 GP_1_1_FN, GPSR1_1,
2118 GP_1_0_FN, GPSR1_0, }
2119 },
2120 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2121 0, 0,
2122 0, 0,
2123 0, 0,
2124 0, 0,
2125 0, 0,
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 GP_2_16_FN, GPSR2_16,
2137 GP_2_15_FN, GPSR2_15,
2138 GP_2_14_FN, GPSR2_14,
2139 GP_2_13_FN, GPSR2_13,
2140 GP_2_12_FN, GPSR2_12,
2141 GP_2_11_FN, GPSR2_11,
2142 GP_2_10_FN, GPSR2_10,
2143 GP_2_9_FN, GPSR2_9,
2144 GP_2_8_FN, GPSR2_8,
2145 GP_2_7_FN, GPSR2_7,
2146 GP_2_6_FN, GPSR2_6,
2147 GP_2_5_FN, GPSR2_5,
2148 GP_2_4_FN, GPSR2_4,
2149 GP_2_3_FN, GPSR2_3,
2150 GP_2_2_FN, GPSR2_2,
2151 GP_2_1_FN, GPSR2_1,
2152 GP_2_0_FN, GPSR2_0, }
2153 },
2154 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2155 0, 0,
2156 0, 0,
2157 0, 0,
2158 0, 0,
2159 0, 0,
2160 0, 0,
2161 0, 0,
2162 0, 0,
2163 0, 0,
2164 0, 0,
2165 0, 0,
2166 0, 0,
2167 0, 0,
2168 0, 0,
2169 0, 0,
2170 GP_3_16_FN, GPSR3_16,
2171 GP_3_15_FN, GPSR3_15,
2172 GP_3_14_FN, GPSR3_14,
2173 GP_3_13_FN, GPSR3_13,
2174 GP_3_12_FN, GPSR3_12,
2175 GP_3_11_FN, GPSR3_11,
2176 GP_3_10_FN, GPSR3_10,
2177 GP_3_9_FN, GPSR3_9,
2178 GP_3_8_FN, GPSR3_8,
2179 GP_3_7_FN, GPSR3_7,
2180 GP_3_6_FN, GPSR3_6,
2181 GP_3_5_FN, GPSR3_5,
2182 GP_3_4_FN, GPSR3_4,
2183 GP_3_3_FN, GPSR3_3,
2184 GP_3_2_FN, GPSR3_2,
2185 GP_3_1_FN, GPSR3_1,
2186 GP_3_0_FN, GPSR3_0, }
2187 },
2188 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2189 0, 0,
2190 0, 0,
2191 0, 0,
2192 0, 0,
2193 0, 0,
2194 0, 0,
2195 0, 0,
2196 0, 0,
2197 0, 0,
2198 0, 0,
2199 0, 0,
2200 0, 0,
2201 0, 0,
2202 0, 0,
2203 0, 0,
2204 0, 0,
2205 0, 0,
2206 0, 0,
2207 0, 0,
2208 0, 0,
2209 0, 0,
2210 0, 0,
2211 0, 0,
2212 0, 0,
2213 0, 0,
2214 0, 0,
2215 GP_4_5_FN, GPSR4_5,
2216 GP_4_4_FN, GPSR4_4,
2217 GP_4_3_FN, GPSR4_3,
2218 GP_4_2_FN, GPSR4_2,
2219 GP_4_1_FN, GPSR4_1,
2220 GP_4_0_FN, GPSR4_0, }
2221 },
2222 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2223 0, 0,
2224 0, 0,
2225 0, 0,
2226 0, 0,
2227 0, 0,
2228 0, 0,
2229 0, 0,
2230 0, 0,
2231 0, 0,
2232 0, 0,
2233 0, 0,
2234 0, 0,
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 0, 0,
2239 0, 0,
2240 GP_5_14_FN, GPSR5_14,
2241 GP_5_13_FN, GPSR5_13,
2242 GP_5_12_FN, GPSR5_12,
2243 GP_5_11_FN, GPSR5_11,
2244 GP_5_10_FN, GPSR5_10,
2245 GP_5_9_FN, GPSR5_9,
2246 GP_5_8_FN, GPSR5_8,
2247 GP_5_7_FN, GPSR5_7,
2248 GP_5_6_FN, GPSR5_6,
2249 GP_5_5_FN, GPSR5_5,
2250 GP_5_4_FN, GPSR5_4,
2251 GP_5_3_FN, GPSR5_3,
2252 GP_5_2_FN, GPSR5_2,
2253 GP_5_1_FN, GPSR5_1,
2254 GP_5_0_FN, GPSR5_0, }
2255 },
2256 #undef F_
2257 #undef FM
2258
2259 #define F_(x, y) x,
2260 #define FM(x) FN_##x,
2261 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2262 IP0_31_28
2263 IP0_27_24
2264 IP0_23_20
2265 IP0_19_16
2266 IP0_15_12
2267 IP0_11_8
2268 IP0_7_4
2269 IP0_3_0 }
2270 },
2271 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2272 IP1_31_28
2273 IP1_27_24
2274 IP1_23_20
2275 IP1_19_16
2276 IP1_15_12
2277 IP1_11_8
2278 IP1_7_4
2279 IP1_3_0 }
2280 },
2281 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2282 IP2_31_28
2283 IP2_27_24
2284 IP2_23_20
2285 IP2_19_16
2286 IP2_15_12
2287 IP2_11_8
2288 IP2_7_4
2289 IP2_3_0 }
2290 },
2291 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2292 IP3_31_28
2293 IP3_27_24
2294 IP3_23_20
2295 IP3_19_16
2296 IP3_15_12
2297 IP3_11_8
2298 IP3_7_4
2299 IP3_3_0 }
2300 },
2301 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2302 IP4_31_28
2303 IP4_27_24
2304 IP4_23_20
2305 IP4_19_16
2306 IP4_15_12
2307 IP4_11_8
2308 IP4_7_4
2309 IP4_3_0 }
2310 },
2311 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2312 IP5_31_28
2313 IP5_27_24
2314 IP5_23_20
2315 IP5_19_16
2316 IP5_15_12
2317 IP5_11_8
2318 IP5_7_4
2319 IP5_3_0 }
2320 },
2321 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2322 IP6_31_28
2323 IP6_27_24
2324 IP6_23_20
2325 IP6_19_16
2326 IP6_15_12
2327 IP6_11_8
2328 IP6_7_4
2329 IP6_3_0 }
2330 },
2331 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2332 IP7_31_28
2333 IP7_27_24
2334 IP7_23_20
2335 IP7_19_16
2336 IP7_15_12
2337 IP7_11_8
2338 IP7_7_4
2339 IP7_3_0 }
2340 },
2341 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2342 IP8_31_28
2343 IP8_27_24
2344 IP8_23_20
2345 IP8_19_16
2346 IP8_15_12
2347 IP8_11_8
2348 IP8_7_4
2349 IP8_3_0 }
2350 },
2351 #undef F_
2352 #undef FM
2353
2354 #define F_(x, y) x,
2355 #define FM(x) FN_##x,
2356 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2357 4, 4, 4, 4,
2358 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2359 /* RESERVED 31, 30, 29, 28 */
2360 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2361 /* RESERVED 27, 26, 25, 24 */
2362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2363 /* RESERVED 23, 22, 21, 20 */
2364 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2365 /* RESERVED 19, 18, 17, 16 */
2366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2367 /* RESERVED 15, 14, 13, 12 */
2368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2369 MOD_SEL0_11
2370 MOD_SEL0_10
2371 MOD_SEL0_9
2372 MOD_SEL0_8
2373 MOD_SEL0_7
2374 MOD_SEL0_6
2375 MOD_SEL0_5
2376 MOD_SEL0_4
2377 MOD_SEL0_3
2378 MOD_SEL0_2
2379 MOD_SEL0_1
2380 MOD_SEL0_0 }
2381 },
2382 { },
2383 };
2384
2385 enum ioctrl_regs {
2386 IOCTRL30,
2387 IOCTRL31,
2388 IOCTRL32,
2389 };
2390
2391 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2392 [IOCTRL30] = { 0xe6060380 },
2393 [IOCTRL31] = { 0xe6060384 },
2394 [IOCTRL32] = { 0xe6060388 },
2395 { /* sentinel */ },
2396 };
2397
r8a77970_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)2398 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2399 u32 *pocctrl)
2400 {
2401 int bit = pin & 0x1f;
2402
2403 *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
2404 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2405 return bit;
2406 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2407 return bit + 22;
2408
2409 *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
2410 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2411 return bit - 10;
2412 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2413 return bit + 7;
2414
2415 return -EINVAL;
2416 }
2417
2418 static const struct sh_pfc_soc_operations pinmux_ops = {
2419 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2420 };
2421
2422 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2423 .name = "r8a77970_pfc",
2424 .ops = &pinmux_ops,
2425 .unlock_reg = 0xe6060000, /* PMMR */
2426
2427 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2428
2429 .pins = pinmux_pins,
2430 .nr_pins = ARRAY_SIZE(pinmux_pins),
2431 .groups = pinmux_groups,
2432 .nr_groups = ARRAY_SIZE(pinmux_groups),
2433 .functions = pinmux_functions,
2434 .nr_functions = ARRAY_SIZE(pinmux_functions),
2435
2436 .cfg_regs = pinmux_config_regs,
2437 .ioctrl_regs = pinmux_ioctrl_regs,
2438
2439 .pinmux_data = pinmux_data,
2440 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2441 };
2442
