Home
last modified time | relevance | path

Searched refs:vgpu_vreg (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dedid.c125 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in gmbus0_mmio_write()
127 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK; in gmbus0_mmio_write()
164 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) { in gmbus1_mmio_write()
166 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT; in gmbus1_mmio_write()
219 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset)) in gmbus1_mmio_write()
253 vgpu_vreg(vgpu, offset) = wvalue; in gmbus1_mmio_write()
279 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read()
290 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count); in gmbus3_mmio_read()
291 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read()
312 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read()
[all …]
Dinterrupt.c182 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler()
183 (vgpu_vreg(vgpu, reg) ^ imr)); in intel_vgpu_reg_imr_handler()
185 vgpu_vreg(vgpu, reg) = imr; in intel_vgpu_reg_imr_handler()
211 u32 virtual_ier = vgpu_vreg(vgpu, reg); in intel_vgpu_reg_master_irq_handler()
223 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; in intel_vgpu_reg_master_irq_handler()
224 vgpu_vreg(vgpu, reg) |= ier; in intel_vgpu_reg_master_irq_handler()
252 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_ier_handler()
253 (vgpu_vreg(vgpu, reg) ^ ier)); in intel_vgpu_reg_ier_handler()
255 vgpu_vreg(vgpu, reg) = ier; in intel_vgpu_reg_ier_handler()
289 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler()
[all …]
Dhandlers.c73 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in read_vreg()
79 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in write_vreg()
281 old = vgpu_vreg(vgpu, offset); in mul_force_wake_write()
306 vgpu_vreg(vgpu, offset) = new; in mul_force_wake_write()
307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write()
318 data = vgpu_vreg(vgpu, offset); in gdrst_mmio_write()
351 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
373 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { in pch_pp_control_mmio_write()
391 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) in transconf_mmio_write()
392 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; in transconf_mmio_write()
[all …]
Dexeclist.c101 status.ldw = vgpu_vreg(vgpu, status_reg); in emulate_execlist_status()
102 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status()
120 vgpu_vreg(vgpu, status_reg) = status.ldw; in emulate_execlist_status()
121 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status()
144 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg); in emulate_csb_update()
157 vgpu_vreg(vgpu, offset) = status->ldw; in emulate_csb_update()
158 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update()
161 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; in emulate_csb_update()
270 status.ldw = vgpu_vreg(vgpu, status_reg); in get_next_execlist_slot()
271 status.udw = vgpu_vreg(vgpu, status_reg + 4); in get_next_execlist_slot()
[all …]
Ddisplay.c40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe()
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled()
Ddebugfs.c67 vreg = vgpu_vreg(param->vgpu, offset); in mmio_diff_handler()
Dscheduler.c213 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
217 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
Dgvt.h446 #define vgpu_vreg(vgpu, offset) \ macro
Dcmd_parser.c857 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); in mocs_cmd_reg_handler()
917 vgpu_vreg(vgpu, offset) = data; in cmd_reg_handler()