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Searched refs:to_intel_crtc_state (Results 1 – 10 of 10) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_color.c142 struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state); in ilk_load_csc_matrix()
358 to_intel_crtc_state(crtc_state)); in i9xx_load_luts()
369 to_intel_crtc_state(crtc_state); in haswell_load_luts()
472 struct intel_crtc_state *intel_state = to_intel_crtc_state(state); in broadwell_load_luts()
530 struct intel_crtc_state *intel_state = to_intel_crtc_state(state); in glk_load_luts()
562 to_intel_crtc_state(state)); in cherryview_load_luts()
605 i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state)); in cherryview_load_luts()
Dintel_atomic_plane.c212 return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state), in intel_plane_atomic_check()
213 to_intel_crtc_state(new_crtc_state), in intel_plane_atomic_check()
Dintel_display.c2775 to_intel_crtc_state(crtc->base.state); in intel_plane_disable_noatomic()
2888 intel_set_plane_visible(to_intel_crtc_state(crtc_state), in intel_find_initial_plane_obj()
5166 hsw_disable_ips(to_intel_crtc_state(crtc->state)); in intel_pre_disable_primary_noatomic()
10516 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); in intel_plane_atomic_calc_changes()
10531 to_intel_crtc_state(crtc_state), in intel_plane_atomic_calc_changes()
10555 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); in intel_plane_atomic_calc_changes()
10653 to_intel_crtc_state(crtc_state); in intel_crtc_atomic_check()
11636 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; in verify_wm_state()
11832 pipe_config = to_intel_crtc_state(old_crtc_state); in verify_crtc_state()
11876 sw_config = to_intel_crtc_state(new_crtc_state); in verify_crtc_state()
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Dintel_dp_mst.c118 slots = to_intel_crtc_state(crtc_state)->dp_m_n.tu; in intel_dp_mst_atomic_check()
130 to_intel_crtc_state(crtc_state)->dp_m_n.tu = 0; in intel_dp_mst_atomic_check()
Dintel_display.h367 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
Dintel_drv.h1001 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) macro
1335 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, in intel_atomic_get_old_crtc_state()
1343 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, in intel_atomic_get_new_crtc_state()
2144 return to_intel_crtc_state(crtc_state); in intel_atomic_get_crtc_state()
Dintel_pm.c3737 cstate = to_intel_crtc_state(crtc->base.state); in intel_can_enable_sagv()
3848 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; in skl_ddb_get_pipe_allocation_limits()
5059 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate); in skl_update_pipe_wm()
5316 to_intel_crtc_state(cstate); in skl_compute_wm()
5318 &to_intel_crtc_state(crtc->state)->wm.skl.optimal; in skl_compute_wm()
5525 cstate = to_intel_crtc_state(crtc->state); in skl_wm_get_hw_state()
5552 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); in ilk_pipe_wm_get_hw_state()
5717 to_intel_crtc_state(crtc->base.state); in g4x_wm_get_hw_state()
5801 to_intel_crtc_state(crtc->base.state); in g4x_wm_sanitize()
5834 to_intel_crtc_state(crtc->base.state); in g4x_wm_sanitize()
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Di915_debugfs.c3159 pipe_config = to_intel_crtc_state(intel_crtc->base.state); in intel_scaler_info()
3196 pipe_config = to_intel_crtc_state(crtc->base.state); in i915_display_info()
3468 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { in drrs_status_per_crtc()
4659 crtc_state = to_intel_crtc_state(intel_crtc->base.state); in i915_fifo_underrun_reset_write()
Dintel_ddi.c3396 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_hdmi_reset_link()
Dintel_dp.c4194 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()