Searched refs:to_intel_atomic_state (Results 1 – 7 of 7) sorted by relevance
233 struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state); in intel_atomic_setup_scalers()380 struct intel_atomic_state *state = to_intel_atomic_state(s); in intel_atomic_state_clear()
2230 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in intel_compute_min_cdclk()2295 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in vlv_modeset_calc_cdclk()2324 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in bdw_modeset_calc_cdclk()2393 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in skl_modeset_calc_cdclk()2431 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in bxt_modeset_calc_cdclk()2475 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in cnl_modeset_calc_cdclk()2510 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in icl_modeset_calc_cdclk()
221 struct intel_atomic_state *state = to_intel_atomic_state(old_state->state); in intel_plane_atomic_update()
1316 to_intel_atomic_state(crtc_state->base.state); in g4x_compute_pipe_wm()1408 to_intel_atomic_state(new_crtc_state->base.state); in g4x_compute_intermediate_wm()1836 to_intel_atomic_state(crtc_state->base.state); in vlv_compute_pipe_wm()2041 to_intel_atomic_state(new_crtc_state->base.state); in vlv_compute_intermediate_wm()2775 to_intel_atomic_state(cstate->base.state); in hsw_compute_linetime_wm()3140 to_intel_atomic_state(newstate->base.state); in ilk_compute_intermediate_wm()3705 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in intel_can_enable_sagv()3814 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); in skl_ddb_get_pipe_allocation_limits()4086 dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; in skl_check_pipe_max_pixel_rate()4491 to_intel_atomic_state(cstate->base.state); in skl_compute_plane_wm_params()[all …]
3705 to_intel_atomic_state(state)->skip_intermediate_wm = true; in __intel_display_resume()5237 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state), in intel_post_plane_update()5283 to_intel_atomic_state(old_state); in intel_pre_plane_update()5510 to_intel_atomic_state(old_state); in ironlake_crtc_enable()5638 to_intel_atomic_state(old_state); in haswell_crtc_enable()5988 to_intel_atomic_state(old_state); in valleyview_crtc_enable()6056 to_intel_atomic_state(old_state); in i9xx_crtc_enable()6522 to_intel_atomic_state(crtc_state->base.state); in hsw_compute_ips_config()9196 to_intel_atomic_state(crtc_state->base.state); in haswell_crtc_compute_clock()10692 !to_intel_atomic_state(state)->skip_intermediate_wm) { in intel_crtc_atomic_check()[all …]
62 struct intel_atomic_state *state = to_intel_atomic_state(s); in intel_atomic_get_shared_dpll_state()327 if (!to_intel_atomic_state(state)->dpll_set) in intel_shared_dpll_swap_state()330 shared_dpll = to_intel_atomic_state(state)->shared_dpll; in intel_shared_dpll_swap_state()
999 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) macro
