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Searched refs:tile (Results 1 – 25 of 72) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
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Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
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Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
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Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
137 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
138 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
166 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
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Dnv49.c33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
Dnv47.c33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
Dnv1a.c31 .tile.regions = 8,
32 .tile.init = nv10_fb_tile_init,
33 .tile.fini = nv10_fb_tile_fini,
34 .tile.prog = nv10_fb_tile_prog,
Dnv4e.c32 .tile.regions = 12,
33 .tile.init = nv46_fb_tile_init,
34 .tile.fini = nv20_fb_tile_fini,
35 .tile.prog = nv44_fb_tile_prog,
/Linux-v4.19/drivers/gpu/drm/i915/selftests/
Di915_gem_object.c144 struct tile { struct
158 static u64 tiled_offset(const struct tile *tile, u64 v) in tiled_offset() argument
162 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
165 y = div64_u64_rem(v, tile->stride, &x); in tiled_offset()
166 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
168 if (tile->tiling == I915_TILING_X) { in tiled_offset()
169 v += y * tile->width; in tiled_offset()
170 v += div64_u64_rem(x, tile->width, &x) << tile->size; in tiled_offset()
172 } else if (tile->width == 128) { in tiled_offset()
188 switch (tile->swizzle) { in tiled_offset()
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/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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Dnv40.c173 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv40_gr_tile() argument
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
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Dbase.c38 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
41 if (gr->func->tile) in nvkm_gr_tile()
42 gr->func->tile(gr, region, tile); in nvkm_gr_tile()
143 .tile = nvkm_gr_tile,
/Linux-v4.19/drivers/gpu/ipu-v3/
Dipu-image-convert.c111 struct ipu_image_tile tile[MAX_TILES]; member
308 ic_image->tile[0].width, ic_image->tile[0].height, in dump_format()
370 struct ipu_image_tile *tile = &image->tile[i]; in calc_tile_dimensions() local
372 tile->height = image->base.pix.height / image->num_rows; in calc_tile_dimensions()
373 tile->width = image->base.pix.width / image->num_cols; in calc_tile_dimensions()
374 tile->size = ((tile->height * image->fmt->bpp) >> 3) * in calc_tile_dimensions()
375 tile->width; in calc_tile_dimensions()
378 tile->stride = tile->width; in calc_tile_dimensions()
379 tile->rot_stride = tile->height; in calc_tile_dimensions()
381 tile->stride = in calc_tile_dimensions()
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/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Damdgpu_acp.c120 static int acp_suspend_tile(void *cgs_dev, int tile) in acp_suspend_tile() argument
125 if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { in acp_suspend_tile()
126 pr_err("Invalid ACP tile : %d to suspend\n", tile); in acp_suspend_tile()
130 val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); in acp_suspend_tile()
135 val = val | (1 << tile); in acp_suspend_tile()
138 0x500 + tile); in acp_suspend_tile()
143 + tile); in acp_suspend_tile()
163 static int acp_resume_tile(void *cgs_dev, int tile) in acp_resume_tile() argument
168 if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { in acp_resume_tile()
173 val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); in acp_resume_tile()
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Dgfx_v7_0.c1029 uint32_t *tile, *macrotile; in gfx_v7_0_tiling_mode_table_init() local
1031 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1048 tile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1054 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1058 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1062 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1066 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1070 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1074 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1077 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
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/Linux-v4.19/Documentation/devicetree/bindings/arm/
Dvexpress.txt8 The motherboard and each core tile should be described by a separate
9 Device Tree source file, with the tile's description including
21 where <model> is the full tile model name (as used in the tile's
27 If a tile comes in several variants or can be used in more then one
40 - tile model name (use name from the tile's Technical Reference
43 - tile's HBI number (unique ARM's board model ID, visible on the
106 0xf means "master" site (site containing main CPU tile)
123 between the motherboard and the tile. The first cell defines the Chip
125 All interrupt lines between the motherboard and the tile are active
140 can be used to obtain required phandle in the tile's "aliases" node:
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/Linux-v4.19/drivers/hid/
Dhid-picolcd_fb.c101 int chip, int tile) in picolcd_fb_send_tile() argument
124 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
137 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
152 int chip, int tile) in picolcd_fb_update_tile() argument
156 u8 *vdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_update_tile()
160 const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; in picolcd_fb_update_tile()
168 const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; in picolcd_fb_update_tile()
237 int chip, tile, n; in picolcd_fb_update() local
258 for (tile = 0; tile < 8; tile++) { in picolcd_fb_update()
261 fbdata->bpp, chip, tile)) in picolcd_fb_update()
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/Linux-v4.19/drivers/gpu/drm/nouveau/
Dnouveau_bo.c56 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
62 if (tile->pitch) in nv10_bo_update_tile_region()
63 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
68 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
77 spin_lock(&drm->tile.lock); in nv10_bo_get_tile_region()
79 if (!tile->used && in nv10_bo_get_tile_region()
80 (!tile->fence || nouveau_fence_done(tile->fence))) in nv10_bo_get_tile_region()
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