Searched refs:tier (Results 1 – 9 of 9) sorted by relevance
19 - systemport,num-tier2-arb: number of tier 2 arbiters, an integer20 - systemport,num-tier1-arb: number of tier 1 arbiters, an integer
53 The lower tier consists of a single dm multipath device for each member.60 The upper tier consists of a single dm-switch device. This device uses62 lower tier device to route the I/O. By using a bitmap we are able to
35 u32 tier; /* Interrupt Enable Register */ member172 tmu_write(data, TIER_DISABLE, &data->regs->tier); in qoriq_tmu_init_device()
107 writel_relaxed(timer->context.tier, timer->irq_ena); in omap_timer_restore_context()694 timer->context.tier = value; in omap_dm_timer_set_int_enable()724 timer->context.tier &= ~mask; in omap_dm_timer_set_int_disable()
78 u32 tier; member
441 u8 tier; member
1466 p_hevc->tier = 0; in s5p_mfc_set_enc_params_hevc()1478 reg |= (p_hevc->tier << 16); in s5p_mfc_set_enc_params_hevc()
2104 p->codec.hevc.tier = ctrl->val; in s5p_mfc_enc_s_ctrl()
2200 .. _v4l2-hevc-tier:2208 rate. Setting the flag to 0 selects HEVC tier as Main tier and setting2209 this flag to 1 indicates High tier. High tier is for applications requiring2223 - Main tier.2225 - High tier.
