Home
last modified time | relevance | path

Searched refs:tf_mask (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
150 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
152 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
245 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
247 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
292 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
294 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
296 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
298 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
301 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
[all …]
Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
482 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp1_dppclk_control()
534 const struct dcn_dpp_mask *tf_mask) in dpp1_construct() argument
544 dpp->tf_mask = tf_mask; in dpp1_construct()
Ddcn10_dpp_dscl.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
376 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp1_dscl_set_scl_filter()
Ddcn10_resource.c393 static const struct dcn_dpp_mask tf_mask = { variable
560 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
Ddcn10_dpp.h1349 const struct dcn_dpp_mask *tf_mask; member
1506 const struct dcn_dpp_mask *tf_mask);