Searched refs:tc_cfg (Results 1 – 5 of 5) sorted by relevance
156 struct qlcnic_dcb_tc_cfg tc_cfg[QLC_DCB_MAX_TC]; member660 struct qlcnic_dcb_tc_cfg *tc_cfg; in qlcnic_dcb_fill_cee_tc_params() local665 tc_cfg = &type->tc_cfg[tc]; in qlcnic_dcb_fill_cee_tc_params()666 tc_cfg->valid = true; in qlcnic_dcb_fill_cee_tc_params()667 tc_cfg->up_tc_map |= QLC_DCB_GET_MAP(i); in qlcnic_dcb_fill_cee_tc_params()671 tc_cfg->prio_cfg[i].valid = true; in qlcnic_dcb_fill_cee_tc_params()672 tc_cfg->prio_cfg[i].pfc_type = QLC_PFC_FULL; in qlcnic_dcb_fill_cee_tc_params()680 tc_cfg->pgid = pgid; in qlcnic_dcb_fill_cee_tc_params()682 tc_cfg->prio_type = QLC_PRIO_LINK; in qlcnic_dcb_fill_cee_tc_params()683 type->pg_cfg[tc_cfg->pgid].prio_count++; in qlcnic_dcb_fill_cee_tc_params()[all …]
390 struct dpu_hw_tear_check tc_cfg = { 0 }; in dpu_encoder_phys_cmd_tearcheck_config() local434 tc_cfg.vsync_count = vsync_hz / (mode->vtotal * mode->vrefresh); in dpu_encoder_phys_cmd_tearcheck_config()437 tc_cfg.hw_vsync_mode = 0; in dpu_encoder_phys_cmd_tearcheck_config()444 tc_cfg.sync_cfg_height = 0xFFF0; in dpu_encoder_phys_cmd_tearcheck_config()445 tc_cfg.vsync_init_val = mode->vdisplay; in dpu_encoder_phys_cmd_tearcheck_config()446 tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START; in dpu_encoder_phys_cmd_tearcheck_config()447 tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE; in dpu_encoder_phys_cmd_tearcheck_config()448 tc_cfg.start_pos = mode->vdisplay; in dpu_encoder_phys_cmd_tearcheck_config()449 tc_cfg.rd_ptr_irq = mode->vdisplay + 1; in dpu_encoder_phys_cmd_tearcheck_config()457 phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos, in dpu_encoder_phys_cmd_tearcheck_config()[all …]
213 struct ice_tc_cfg tc_cfg; member307 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS; in ice_vsi_set_tc_cfg()308 vsi->tc_cfg.numtc = 1; in ice_vsi_set_tc_cfg()
1277 if (vsi->tc_cfg.numtc) { in ice_vsi_setup_q_map()1278 if (!(vsi->tc_cfg.ena_tc & BIT(0))) in ice_vsi_setup_q_map()1285 vsi->tc_cfg.numtc++; in ice_vsi_setup_q_map()1286 vsi->tc_cfg.ena_tc |= 1; in ice_vsi_setup_q_map()1289 numq_tc = qcount_rx / vsi->tc_cfg.numtc; in ice_vsi_setup_q_map()1320 if (!(vsi->tc_cfg.ena_tc & BIT(i))) { in ice_vsi_setup_q_map()1322 vsi->tc_cfg.tc_info[i].qoffset = 0; in ice_vsi_setup_q_map()1323 vsi->tc_cfg.tc_info[i].qcount = 1; in ice_vsi_setup_q_map()1329 vsi->tc_cfg.tc_info[i].qoffset = offset; in ice_vsi_setup_q_map()1330 vsi->tc_cfg.tc_info[i].qcount = qcount; in ice_vsi_setup_q_map()[all …]
1219 u32 tc_cfg; in hns_dsaf_inode_init() local1223 tc_cfg = HNS_DSAF_I4TC_CFG; in hns_dsaf_inode_init()1225 tc_cfg = HNS_DSAF_I8TC_CFG; in hns_dsaf_inode_init()1260 dsaf_write_dev(dsaf_dev, reg, tc_cfg); in hns_dsaf_inode_init()
