Home
last modified time | relevance | path

Searched refs:t9 (Results 1 – 22 of 22) sorted by relevance

/Linux-v4.19/arch/mips/kernel/
Dcps-vec.S178 move a1, t9
322 li t9, 0
331 mfc0 t9, CP0_GLOBALNUMBER
332 andi t9, t9, MIPS_GLOBALNUMBER_VP
351 mfc0 t9, $15, 1
352 and t9, t9, t1
357 mul v1, t9, t1
Docteon_switch.S49 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
54 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
66 LONG_L t9, TASK_STACK_CANARY(a1)
67 LONG_S t9, 0(t8)
100 dmfc0 t9, $9,7 /* CvmCtl register. */
109 bbit1 t9, 28, 1f
117 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
263 dmfc0 t9, $9,7 /* CvmCtl register. */
274 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
284 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
Dr4k_switch.S36 LONG_L t9, TASK_STACK_CANARY(a1)
37 LONG_S t9, 0(t8)
Dr2300_switch.S41 LONG_L t9, TASK_STACK_CANARY(a1)
42 LONG_S t9, 0(t8)
Dcps-vec-ns16550.S27 1: lw t0, UART_LSR_OFS(t9)
30 sb a0, UART_TX_OFS(t9)
166 li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
Dpm-cps.c80 t8, t9, k0, k1, gp, sp, fp, ra, enumerator
/Linux-v4.19/arch/mips/include/asm/
Dregdef.h51 #define t9 $25 macro
94 #define t9 $25 /* callee address for PIC/temp */ macro
/Linux-v4.19/arch/ia64/lib/
Dcopy_page_mck.S84 #define t9 t5 // alias! macro
163 (p[D]) ld8 t9 = [src0], 3*8
170 (p[D]) st8 [dst0] = t9, 3*8
Dmemcpy_mck.S53 #define t9 t5 // alias! macro
243 EX(.ex_handler, (p[D]) ld8 t9 = [src0], 3*8)
250 EX(.ex_handler, (p[D]) st8 [dst0] = t9, 3*8)
/Linux-v4.19/arch/alpha/lib/
Dstxcpy.S39 .frame sp, 0, t9
91 ret (t9) # .. e1 :
99 .frame sp, 0, t9
230 ret (t9) # .. e1 :
288 ret (t9) # e1 :
Dev6-stxcpy.S50 .frame sp, 0, t9
109 ret (t9) # L0 : Latency=3
119 .frame sp, 0, t9
259 ret (t9) # L0 : Latency=3
318 ret (t9) # e1 :
Dstxncpy.S47 .frame sp, 0, t9, 0
105 ret (t9) # e1 :
118 .frame sp, 0, t9, 0
266 ret (t9) # .. e1 :
344 ret (t9) # .. e1 :
Dev6-stxncpy.S58 .frame sp, 0, t9, 0
133 ret (t9) # L0 : Latency=3
150 .frame sp, 0, t9, 0
312 ret (t9) # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
/Linux-v4.19/arch/arm64/crypto/
Dghash-ce-core.S33 t9 .req v16
108 pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
117 uzp1 t6.2d, t7.2d, t9.2d
118 uzp2 t7.2d, t7.2d, t9.2d
135 zip2 t9.2d, t6.2d, t7.2d
141 ext t9.16b, t9.16b, t9.16b, #12
144 eor t7.16b, t7.16b, t9.16b
/Linux-v4.19/arch/alpha/include/uapi/asm/
Dregdef.h33 #define t9 $23 macro
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_bios.h44 u16 t9; member
Dintel_dp.c5409 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> in intel_pps_readout_hw_state()
5430 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
5441 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
5487 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in intel_dp_init_panel_power_sequencer()
5504 assign_final(t9); in intel_dp_init_panel_power_sequencer()
5512 intel_dp->backlight_off_delay = get_delay(t9); in intel_dp_init_panel_power_sequencer()
5532 final->t9 = 1; in intel_dp_init_panel_power_sequencer()
5583 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | in intel_dp_init_panel_power_sequencer_registers()
/Linux-v4.19/arch/mips/lib/
Dmemset.S102 move t9, a1
Dcsum_partial.S323 #define errptr t9
/Linux-v4.19/drivers/gpu/drm/gma500/
Dintel_bios.h461 u16 t9; member
Dintel_bios.c97 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
Dcdv_intel_dp.c2090 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> in cdv_intel_dp_init()
2100 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); in cdv_intel_dp_init()
2105 intel_dp->backlight_off_delay = cur.t9 / 10; in cdv_intel_dp_init()