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Searched refs:ss_clk (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/usb/host/
Dxhci-tegra.c186 struct clk *ss_clk; member
679 err = clk_prepare_enable(tegra->ss_clk); in tegra_xusb_clk_enable()
710 clk_disable_unprepare(tegra->ss_clk); in tegra_xusb_clk_enable()
722 clk_disable_unprepare(tegra->ss_clk); in tegra_xusb_clk_disable()
992 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); in tegra_xusb_probe()
993 if (IS_ERR(tegra->ss_clk)) { in tegra_xusb_probe()
994 err = PTR_ERR(tegra->ss_clk); in tegra_xusb_probe()
1060 tegra->ss_clk, in tegra_xusb_probe()
/Linux-v4.19/Documentation/devicetree/bindings/crypto/
Dsun4i-ss.txt21 clocks = <&ahb_gates 5>, <&ss_clk>;
/Linux-v4.19/drivers/clk/sunxi-ng/
Dccu-sun5i.c369 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
578 &ss_clk.common,
695 [CLK_SS] = &ss_clk.common.hw,
828 [CLK_SS] = &ss_clk.common.hw,
939 [CLK_SS] = &ss_clk.common.hw,
Dccu-sun8i-a33.c345 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
545 &ss_clk.common,
664 [CLK_SS] = &ss_clk.common.hw,
Dccu-sun8i-a83t.c440 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents,
663 &ss_clk.common,
768 [CLK_SS] = &ss_clk.common.hw,
Dccu-sun9i-a80.c494 static struct ccu_mp ss_clk = { variable
879 &ss_clk.common,
1025 [CLK_SS] = &ss_clk.common.hw,
Dccu-sun4i-a10.c529 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
972 &ss_clk.common,
1149 [CLK_SS] = &ss_clk.common.hw,
1315 [CLK_SS] = &ss_clk.common.hw,
Dccu-sun6i-a31.c442 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
898 &ss_clk.common,
1075 [CLK_SS] = &ss_clk.common.hw,