Searched refs:speculative (Results 1 – 25 of 26) sorted by relevance
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59 cttz t0, a2 # U0 : speculative (in case we get a match)76 cttz t3, a2 # U0 : speculative (in case we get a match)
166 addq $5, 128, $4 # E : speculative target of next wh64344 addq $5, 128, $4 # E : speculative target of next wh64532 addq $5, 128, $4 # E : speculative target of next wh64
9 employ speculative execution techniques such as branch prediction, performing12 Typically speculative execution cannot be observed from architectural state,
371 deferral and combination of memory operations; speculative loads; speculative2805 displace a dirty cacheline or to do a speculative load;
349 speculative-read|speculative-load |
62 are speculative[2], so the processor can read any location in the71 Uncacheable mappings are not speculative, so the processor will181 WB-only memory, but since UC is non-speculative, the processor will
232 handler performed a speculative load that gets NaTted. If so, this
74 This enables support for a speculative instruction fetch for
290 xgr %r1,%r1 # prevent speculative use336 # clear user controlled register to prevent speculative use619 # clear user controlled registers to prevent speculative use694 # clear user controlled registers to prevent speculative use922 # clear user controlled registers to prevent speculative use1143 # clear user controlled registers to prevent speculative use
5 It depends. Fast eMMC and multiple cache levels with speculative cache
21 unused speculative allocations are of course freed, but if the
58 nor permit speculative access to it under any circumstances other
5 speculative access to data which is available in the Level 1 Data Cache48 then speculative execution ignores the invalid PTE and loads the referenced52 While this is a purely speculative mechanism and the instruction will raise54 data and making it available to other speculative instructions opens up the
560 regard to speculative execution.572 prompt "Avoid speculative indirect branches in the kernel"575 against kernel-to-user data leaks by avoiding speculative indirect
2845 gfn_t gfn, kvm_pfn_t pfn, bool speculative, in set_spte() argument2866 if (!speculative) in set_spte()2930 if (speculative) in set_spte()2942 bool speculative, bool host_writable) in mmu_set_spte() argument2976 speculative, true, host_writable); in mmu_set_spte()
396 유예, 메모리 오퍼레이션들의 조합, 예측적 로드(speculative load), 브랜치397 예측(speculative branch prediction), 다양한 종류의 캐싱(caching) 등의 다양한
373 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19),374 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
914 not perform speculative loads into the D-cache. For such1087 on ARMv6 CPUs, but since they do not have aggressive speculative
262 with unused speculative preallocation runs. The scan
389 The Remus HA project uses this module to enable speculative execution
942 by speculative loads.
435 bool "Avoid speculative indirect branches in kernel"440 kernel-to-user data leaks by avoiding speculative indirect
1084 r3p*) erratum. A speculative memory access may cause a page table walk
1466 speculative execution of BPF instructions by the interpreter
3504 of the CPU relating to speculative execution of instructions and3505 possible information leakage resulting from speculative execution (see
