Searched refs:soc_readl (Results 1 – 6 of 6) sorted by relevance
69 ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)82 u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK; in timer64_config()99 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr); in timer64_enable()103 val = soc_readl(&timer->tcr); in timer64_enable()107 val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK; in timer64_enable()115 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr); in timer64_disable()
75 soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask); in mask_megamod()86 soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask); in unmask_megamod()109 while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) { in megamod_irq_cascade()159 val = soc_readl(&pic->regs->intmux[index]); in set_megamod_mux()317 mask = soc_readl(&mm_pic->regs->mexpflag[i]); in get_exception()
230 val = soc_readl(dscr.base + ctl->reg); in dscr_set_devstate()249 val = soc_readl(dscr.base + stat->reg); in dscr_set_devstate()274 val = soc_readl(dscr.base + r->reg); in dscr_rmii_reset()292 c6x_devstat = soc_readl(base + val); in dscr_parse_devstat()304 c6x_silicon_rev = soc_readl(base + vals[0]); in dscr_parse_silicon_rev()339 fuse = soc_readl(base + vals[f * 5]); in dscr_parse_mac_fuse()
112 #define imcr_get(reg) soc_readl(cache_base + (reg))116 soc_readl(cache_base + (reg)); \
206 return soc_readl(pll->base + reg); in pll_read()
32 #define soc_readl(addr) __raw_readl(addr) macro
