Searched refs:seq_state (Results 1 – 7 of 7) sorted by relevance
938 const char *seq_state; in cia_decode_mem_error() local973 seq_state = "Idle"; in cia_decode_mem_error()976 seq_state = "DMA READ or DMA WRITE"; in cia_decode_mem_error()979 seq_state = "READ MISS (or READ MISS MODIFY) with victim"; in cia_decode_mem_error()982 seq_state = "READ MISS (or READ MISS MODIFY) with no victim"; in cia_decode_mem_error()985 seq_state = "Refresh"; in cia_decode_mem_error()988 seq_state = "Idle, waiting for DMA pending read"; in cia_decode_mem_error()991 seq_state = "Idle, ras precharge"; in cia_decode_mem_error()994 seq_state = "Unknown"; in cia_decode_mem_error()1024 printk(KERN_CRIT " Memory sequencer state: %s\n", seq_state); in cia_decode_mem_error()
220 u32 stat, seq_state; in boot_core() local259 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in boot_core()260 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in boot_core()263 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) in boot_core()
259 u32 seq_state; member
225 config->seq_state = 0x0; in reset_store()1280 val = config->seq_state; in seq_state_show()1297 config->seq_state = val; in seq_state_store()1300 static DEVICE_ATTR_RW(seq_state);
120 writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR); in etm4_enable_hw()
895 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_irq_clean_complete() local904 switch (seq_state) { in mcr20a_irq_clean_complete()
189 What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state
