Searched refs:sclk_setting (Results 1 – 3 of 3) sorted by relevance
718 uint32_t clock, SMU_SclkSetting *sclk_setting) in vegam_calculate_sclk_params() argument729 sclk_setting->SclkFrequency = clock; in vegam_calculate_sclk_params()733 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()734 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()735 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()736 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()737 sclk_setting->Sclk_slew_rate = 0x400; in vegam_calculate_sclk_params()738 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()739 sclk_setting->Pcc_down_slew_rate = 0xffff; in vegam_calculate_sclk_params()740 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()[all …]
841 uint32_t clock, SMU_SclkSetting *sclk_setting) in polaris10_calculate_sclk_params() argument852 sclk_setting->SclkFrequency = clock; in polaris10_calculate_sclk_params()856 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()857 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()858 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()859 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()860 sclk_setting->Sclk_slew_rate = 0x400; in polaris10_calculate_sclk_params()861 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()862 sclk_setting->Pcc_down_slew_rate = 0xffff; in polaris10_calculate_sclk_params()863 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()[all …]
2120 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; member
