1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20 #ifndef _PSB_DRV_H_
21 #define _PSB_DRV_H_
22
23 #include <linux/kref.h>
24 #include <linux/mm_types.h>
25
26 #include <drm/drmP.h>
27 #include <drm/drm_global.h>
28 #include <drm/gma_drm.h>
29 #include "psb_reg.h"
30 #include "psb_intel_drv.h"
31 #include "gma_display.h"
32 #include "intel_bios.h"
33 #include "gtt.h"
34 #include "power.h"
35 #include "opregion.h"
36 #include "oaktrail.h"
37 #include "mmu.h"
38
39 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
40
41 #define DRIVER_NAME "gma500"
42 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
43 #define DRIVER_DATE "20140314"
44
45 #define DRIVER_MAJOR 1
46 #define DRIVER_MINOR 0
47 #define DRIVER_PATCHLEVEL 0
48
49 /* Append new drm mode definition here, align with libdrm definition */
50 #define DRM_MODE_SCALE_NO_SCALE 2
51
52 enum {
53 CHIP_PSB_8108 = 0, /* Poulsbo */
54 CHIP_PSB_8109 = 1, /* Poulsbo */
55 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
56 CHIP_MFLD_0130 = 3, /* Medfield */
57 };
58
59 #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
60 #define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
61 #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
62 #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
63
64 /* Hardware offsets */
65 #define PSB_VDC_OFFSET 0x00000000
66 #define PSB_VDC_SIZE 0x000080000
67 #define MRST_MMIO_SIZE 0x0000C0000
68 #define MDFLD_MMIO_SIZE 0x000100000
69 #define PSB_SGX_SIZE 0x8000
70 #define PSB_SGX_OFFSET 0x00040000
71 #define MRST_SGX_OFFSET 0x00080000
72
73 /* PCI resource identifiers */
74 #define PSB_MMIO_RESOURCE 0
75 #define PSB_AUX_RESOURCE 0
76 #define PSB_GATT_RESOURCE 2
77 #define PSB_GTT_RESOURCE 3
78
79 /* PCI configuration */
80 #define PSB_GMCH_CTRL 0x52
81 #define PSB_BSM 0x5C
82 #define _PSB_GMCH_ENABLED 0x4
83 #define PSB_PGETBL_CTL 0x2020
84 #define _PSB_PGETBL_ENABLED 0x00000001
85 #define PSB_SGX_2D_SLAVE_PORT 0x4000
86 #define PSB_LPC_GBA 0x44
87
88 /* TODO: To get rid of */
89 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
90 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
91
92 /* SGX side MMU definitions (these can probably go) */
93
94 /* Flags for external memory type field */
95 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
96 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
97 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
98
99 /* PTE's and PDE's */
100 #define PSB_PDE_MASK 0x003FFFFF
101 #define PSB_PDE_SHIFT 22
102 #define PSB_PTE_SHIFT 12
103
104 /* Cache control */
105 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
106 #define PSB_PTE_WO 0x0002 /* Write only */
107 #define PSB_PTE_RO 0x0004 /* Read only */
108 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
109
110 /* VDC registers and bits */
111 #define PSB_MSVDX_CLOCKGATING 0x2064
112 #define PSB_TOPAZ_CLOCKGATING 0x2068
113 #define PSB_HWSTAM 0x2098
114 #define PSB_INSTPM 0x20C0
115 #define PSB_INT_IDENTITY_R 0x20A4
116 #define _PSB_IRQ_ASLE (1<<0)
117 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
118 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
119 #define _PSB_DPST_PIPEB_FLAG (1<<4)
120 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
121 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
122 #define _PSB_DPST_PIPEA_FLAG (1<<6)
123 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
124 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
125 #define _MDFLD_MIPIA_FLAG (1<<16)
126 #define _MDFLD_MIPIC_FLAG (1<<17)
127 #define _PSB_IRQ_DISP_HOTSYNC (1<<17)
128 #define _PSB_IRQ_SGX_FLAG (1<<18)
129 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
130 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
131
132 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
133 _PSB_VSYNC_PIPEB_FLAG)
134
135 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
136 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
137 _MDFLD_PIPEB_EVENT_FLAG | \
138 _PSB_PIPEA_EVENT_FLAG | \
139 _PSB_VSYNC_PIPEA_FLAG | \
140 _MDFLD_MIPIA_FLAG | \
141 _MDFLD_MIPIC_FLAG)
142 #define PSB_INT_IDENTITY_R 0x20A4
143 #define PSB_INT_MASK_R 0x20A8
144 #define PSB_INT_ENABLE_R 0x20A0
145
146 #define _PSB_MMU_ER_MASK 0x0001FF00
147 #define _PSB_MMU_ER_HOST (1 << 16)
148 #define GPIOA 0x5010
149 #define GPIOB 0x5014
150 #define GPIOC 0x5018
151 #define GPIOD 0x501c
152 #define GPIOE 0x5020
153 #define GPIOF 0x5024
154 #define GPIOG 0x5028
155 #define GPIOH 0x502c
156 #define GPIO_CLOCK_DIR_MASK (1 << 0)
157 #define GPIO_CLOCK_DIR_IN (0 << 1)
158 #define GPIO_CLOCK_DIR_OUT (1 << 1)
159 #define GPIO_CLOCK_VAL_MASK (1 << 2)
160 #define GPIO_CLOCK_VAL_OUT (1 << 3)
161 #define GPIO_CLOCK_VAL_IN (1 << 4)
162 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
163 #define GPIO_DATA_DIR_MASK (1 << 8)
164 #define GPIO_DATA_DIR_IN (0 << 9)
165 #define GPIO_DATA_DIR_OUT (1 << 9)
166 #define GPIO_DATA_VAL_MASK (1 << 10)
167 #define GPIO_DATA_VAL_OUT (1 << 11)
168 #define GPIO_DATA_VAL_IN (1 << 12)
169 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
170
171 #define VCLK_DIVISOR_VGA0 0x6000
172 #define VCLK_DIVISOR_VGA1 0x6004
173 #define VCLK_POST_DIV 0x6010
174
175 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
176 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
177 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
178 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
179 #define PSB_COMM_USER_IRQ (1024 >> 2)
180 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
181 #define PSB_COMM_FW (2048 >> 2)
182
183 #define PSB_UIRQ_VISTEST 1
184 #define PSB_UIRQ_OOM_REPLY 2
185 #define PSB_UIRQ_FIRE_TA_REPLY 3
186 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
187
188 #define PSB_2D_SIZE (256*1024*1024)
189 #define PSB_MAX_RELOC_PAGES 1024
190
191 #define PSB_LOW_REG_OFFS 0x0204
192 #define PSB_HIGH_REG_OFFS 0x0600
193
194 #define PSB_NUM_VBLANKS 2
195
196
197 #define PSB_2D_SIZE (256*1024*1024)
198 #define PSB_MAX_RELOC_PAGES 1024
199
200 #define PSB_LOW_REG_OFFS 0x0204
201 #define PSB_HIGH_REG_OFFS 0x0600
202
203 #define PSB_NUM_VBLANKS 2
204 #define PSB_WATCHDOG_DELAY (HZ * 2)
205 #define PSB_LID_DELAY (HZ / 10)
206
207 #define MDFLD_PNW_B0 0x04
208 #define MDFLD_PNW_C0 0x08
209
210 #define MDFLD_DSR_2D_3D_0 (1 << 0)
211 #define MDFLD_DSR_2D_3D_2 (1 << 1)
212 #define MDFLD_DSR_CURSOR_0 (1 << 2)
213 #define MDFLD_DSR_CURSOR_2 (1 << 3)
214 #define MDFLD_DSR_OVERLAY_0 (1 << 4)
215 #define MDFLD_DSR_OVERLAY_2 (1 << 5)
216 #define MDFLD_DSR_MIPI_CONTROL (1 << 6)
217 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
218 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
219 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
220
221 #define MDFLD_DSR_RR 45
222 #define MDFLD_DPU_ENABLE (1 << 31)
223 #define MDFLD_DSR_FULLSCREEN (1 << 30)
224 #define MDFLD_DSR_DELAY (HZ / MDFLD_DSR_RR)
225
226 #define PSB_PWR_STATE_ON 1
227 #define PSB_PWR_STATE_OFF 2
228
229 #define PSB_PMPOLICY_NOPM 0
230 #define PSB_PMPOLICY_CLOCKGATING 1
231 #define PSB_PMPOLICY_POWERDOWN 2
232
233 #define PSB_PMSTATE_POWERUP 0
234 #define PSB_PMSTATE_CLOCKGATED 1
235 #define PSB_PMSTATE_POWERDOWN 2
236 #define PSB_PCIx_MSI_ADDR_LOC 0x94
237 #define PSB_PCIx_MSI_DATA_LOC 0x98
238
239 /* Medfield crystal settings */
240 #define KSEL_CRYSTAL_19 1
241 #define KSEL_BYPASS_19 5
242 #define KSEL_BYPASS_25 6
243 #define KSEL_BYPASS_83_100 7
244
245 struct opregion_header;
246 struct opregion_acpi;
247 struct opregion_swsci;
248 struct opregion_asle;
249
250 struct psb_intel_opregion {
251 struct opregion_header *header;
252 struct opregion_acpi *acpi;
253 struct opregion_swsci *swsci;
254 struct opregion_asle *asle;
255 void *vbt;
256 u32 __iomem *lid_state;
257 struct work_struct asle_work;
258 };
259
260 struct sdvo_device_mapping {
261 u8 initialized;
262 u8 dvo_port;
263 u8 slave_addr;
264 u8 dvo_wiring;
265 u8 i2c_pin;
266 u8 i2c_speed;
267 u8 ddc_pin;
268 };
269
270 struct intel_gmbus {
271 struct i2c_adapter adapter;
272 struct i2c_adapter *force_bit;
273 u32 reg0;
274 };
275
276 /* Register offset maps */
277 struct psb_offset {
278 u32 fp0;
279 u32 fp1;
280 u32 cntr;
281 u32 conf;
282 u32 src;
283 u32 dpll;
284 u32 dpll_md;
285 u32 htotal;
286 u32 hblank;
287 u32 hsync;
288 u32 vtotal;
289 u32 vblank;
290 u32 vsync;
291 u32 stride;
292 u32 size;
293 u32 pos;
294 u32 surf;
295 u32 addr;
296 u32 base;
297 u32 status;
298 u32 linoff;
299 u32 tileoff;
300 u32 palette;
301 };
302
303 /*
304 * Register save state. This is used to hold the context when the
305 * device is powered off. In the case of Oaktrail this can (but does not
306 * yet) include screen blank. Operations occuring during the save
307 * update the register cache instead.
308 */
309
310 /* Common status for pipes */
311 struct psb_pipe {
312 u32 fp0;
313 u32 fp1;
314 u32 cntr;
315 u32 conf;
316 u32 src;
317 u32 dpll;
318 u32 dpll_md;
319 u32 htotal;
320 u32 hblank;
321 u32 hsync;
322 u32 vtotal;
323 u32 vblank;
324 u32 vsync;
325 u32 stride;
326 u32 size;
327 u32 pos;
328 u32 base;
329 u32 surf;
330 u32 addr;
331 u32 status;
332 u32 linoff;
333 u32 tileoff;
334 u32 palette[256];
335 };
336
337 struct psb_state {
338 uint32_t saveVCLK_DIVISOR_VGA0;
339 uint32_t saveVCLK_DIVISOR_VGA1;
340 uint32_t saveVCLK_POST_DIV;
341 uint32_t saveVGACNTRL;
342 uint32_t saveADPA;
343 uint32_t saveLVDS;
344 uint32_t saveDVOA;
345 uint32_t saveDVOB;
346 uint32_t saveDVOC;
347 uint32_t savePP_ON;
348 uint32_t savePP_OFF;
349 uint32_t savePP_CONTROL;
350 uint32_t savePP_CYCLE;
351 uint32_t savePFIT_CONTROL;
352 uint32_t saveCLOCKGATING;
353 uint32_t saveDSPARB;
354 uint32_t savePFIT_AUTO_RATIOS;
355 uint32_t savePFIT_PGM_RATIOS;
356 uint32_t savePP_ON_DELAYS;
357 uint32_t savePP_OFF_DELAYS;
358 uint32_t savePP_DIVISOR;
359 uint32_t saveBCLRPAT_A;
360 uint32_t saveBCLRPAT_B;
361 uint32_t savePERF_MODE;
362 uint32_t saveDSPFW1;
363 uint32_t saveDSPFW2;
364 uint32_t saveDSPFW3;
365 uint32_t saveDSPFW4;
366 uint32_t saveDSPFW5;
367 uint32_t saveDSPFW6;
368 uint32_t saveCHICKENBIT;
369 uint32_t saveDSPACURSOR_CTRL;
370 uint32_t saveDSPBCURSOR_CTRL;
371 uint32_t saveDSPACURSOR_BASE;
372 uint32_t saveDSPBCURSOR_BASE;
373 uint32_t saveDSPACURSOR_POS;
374 uint32_t saveDSPBCURSOR_POS;
375 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1;
378 uint32_t saveOV_OGAMC2;
379 uint32_t saveOV_OGAMC3;
380 uint32_t saveOV_OGAMC4;
381 uint32_t saveOV_OGAMC5;
382 uint32_t saveOVC_OVADD;
383 uint32_t saveOVC_OGAMC0;
384 uint32_t saveOVC_OGAMC1;
385 uint32_t saveOVC_OGAMC2;
386 uint32_t saveOVC_OGAMC3;
387 uint32_t saveOVC_OGAMC4;
388 uint32_t saveOVC_OGAMC5;
389
390 /* DPST register save */
391 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
392 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
393 uint32_t savePWM_CONTROL_LOGIC;
394 };
395
396 struct medfield_state {
397 uint32_t saveMIPI;
398 uint32_t saveMIPI_C;
399
400 uint32_t savePFIT_CONTROL;
401 uint32_t savePFIT_PGM_RATIOS;
402 uint32_t saveHDMIPHYMISCCTL;
403 uint32_t saveHDMIB_CONTROL;
404 };
405
406 struct cdv_state {
407 uint32_t saveDSPCLK_GATE_D;
408 uint32_t saveRAMCLK_GATE_D;
409 uint32_t saveDSPARB;
410 uint32_t saveDSPFW[6];
411 uint32_t saveADPA;
412 uint32_t savePP_CONTROL;
413 uint32_t savePFIT_PGM_RATIOS;
414 uint32_t saveLVDS;
415 uint32_t savePFIT_CONTROL;
416 uint32_t savePP_ON_DELAYS;
417 uint32_t savePP_OFF_DELAYS;
418 uint32_t savePP_CYCLE;
419 uint32_t saveVGACNTRL;
420 uint32_t saveIER;
421 uint32_t saveIMR;
422 u8 saveLBB;
423 };
424
425 struct psb_save_area {
426 struct psb_pipe pipe[3];
427 uint32_t saveBSM;
428 uint32_t saveVBT;
429 union {
430 struct psb_state psb;
431 struct medfield_state mdfld;
432 struct cdv_state cdv;
433 };
434 uint32_t saveBLC_PWM_CTL2;
435 uint32_t saveBLC_PWM_CTL;
436 };
437
438 struct psb_ops;
439
440 #define PSB_NUM_PIPE 3
441
442 struct drm_psb_private {
443 struct drm_device *dev;
444 struct pci_dev *aux_pdev; /* Currently only used by mrst */
445 struct pci_dev *lpc_pdev; /* Currently only used by mrst */
446 const struct psb_ops *ops;
447 const struct psb_offset *regmap;
448
449 struct child_device_config *child_dev;
450 int child_dev_num;
451
452 struct psb_gtt gtt;
453
454 /* GTT Memory manager */
455 struct psb_gtt_mm *gtt_mm;
456 struct page *scratch_page;
457 u32 __iomem *gtt_map;
458 uint32_t stolen_base;
459 u8 __iomem *vram_addr;
460 unsigned long vram_stolen_size;
461 int gtt_initialized;
462 u16 gmch_ctrl; /* Saved GTT setup */
463 u32 pge_ctl;
464
465 struct mutex gtt_mutex;
466 struct resource *gtt_mem; /* Our PCI resource */
467
468 struct mutex mmap_mutex;
469
470 struct psb_mmu_driver *mmu;
471 struct psb_mmu_pd *pf_pd;
472
473 /* Register base */
474 uint8_t __iomem *sgx_reg;
475 uint8_t __iomem *vdc_reg;
476 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
477 uint16_t lpc_gpio_base;
478 uint32_t gatt_free_offset;
479
480 /* Fencing / irq */
481 uint32_t vdc_irq_mask;
482 uint32_t pipestat[PSB_NUM_PIPE];
483
484 spinlock_t irqmask_lock;
485
486 /* Power */
487 bool suspended;
488 bool display_power;
489 int display_count;
490
491 /* Modesetting */
492 struct psb_intel_mode_device mode_dev;
493 bool modeset; /* true if we have done the mode_device setup */
494
495 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
496 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
497 uint32_t num_pipe;
498
499 /* OSPM info (Power management base) (TODO: can go ?) */
500 uint32_t ospm_base;
501
502 /* Sizes info */
503 u32 fuse_reg_value;
504 u32 video_device_fuse;
505
506 /* PCI revision ID for B0:D2:F0 */
507 uint8_t platform_rev_id;
508
509 /* gmbus */
510 struct intel_gmbus *gmbus;
511 uint8_t __iomem *gmbus_reg;
512
513 /* Used by SDVO */
514 int crt_ddc_pin;
515 /* FIXME: The mappings should be parsed from bios but for now we can
516 pretend there are no mappings available */
517 struct sdvo_device_mapping sdvo_mappings[2];
518 u32 hotplug_supported_mask;
519 struct drm_property *broadcast_rgb_property;
520 struct drm_property *force_audio_property;
521
522 /* LVDS info */
523 int backlight_duty_cycle; /* restore backlight to this value */
524 bool panel_wants_dither;
525 struct drm_display_mode *panel_fixed_mode;
526 struct drm_display_mode *lfp_lvds_vbt_mode;
527 struct drm_display_mode *sdvo_lvds_vbt_mode;
528
529 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
530 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
531
532 /* Feature bits from the VBIOS */
533 unsigned int int_tv_support:1;
534 unsigned int lvds_dither:1;
535 unsigned int lvds_vbt:1;
536 unsigned int int_crt_support:1;
537 unsigned int lvds_use_ssc:1;
538 int lvds_ssc_freq;
539 bool is_lvds_on;
540 bool is_mipi_on;
541 u32 mipi_ctrl_display;
542
543 unsigned int core_freq;
544 uint32_t iLVDS_enable;
545
546 /* Runtime PM state */
547 int rpm_enabled;
548
549 /* MID specific */
550 bool has_gct;
551 struct oaktrail_gct_data gct_data;
552
553 /* Oaktrail HDMI state */
554 struct oaktrail_hdmi_dev *hdmi_priv;
555
556 /* Register state */
557 struct psb_save_area regs;
558
559 /* MSI reg save */
560 uint32_t msi_addr;
561 uint32_t msi_data;
562
563 /* Hotplug handling */
564 struct work_struct hotplug_work;
565
566 /* LID-Switch */
567 spinlock_t lid_lock;
568 struct timer_list lid_timer;
569 struct psb_intel_opregion opregion;
570 u32 lid_last_state;
571
572 /* Watchdog */
573 uint32_t apm_reg;
574 uint16_t apm_base;
575
576 /*
577 * Used for modifying backlight from
578 * xrandr -- consider removing and using HAL instead
579 */
580 struct backlight_device *backlight_device;
581 struct drm_property *backlight_property;
582 bool backlight_enabled;
583 int backlight_level;
584 uint32_t blc_adj1;
585 uint32_t blc_adj2;
586
587 void *fbdev;
588
589 /* 2D acceleration */
590 spinlock_t lock_2d;
591
592 /* Panel brightness */
593 int brightness;
594 int brightness_adjusted;
595
596 bool dsr_enable;
597 u32 dsr_fb_update;
598 bool dpi_panel_on[3];
599 void *dsi_configs[2];
600 u32 bpp;
601 u32 bpp2;
602
603 u32 pipeconf[3];
604 u32 dspcntr[3];
605
606 int mdfld_panel_id;
607
608 bool dplla_96mhz; /* DPLL data from the VBT */
609
610 struct {
611 int rate;
612 int lanes;
613 int preemphasis;
614 int vswing;
615
616 bool initialized;
617 bool support;
618 int bpp;
619 struct edp_power_seq pps;
620 } edp;
621 uint8_t panel_type;
622 };
623
624
625 /* Operations for each board type */
626 struct psb_ops {
627 const char *name;
628 unsigned int accel_2d:1;
629 int pipes; /* Number of output pipes */
630 int crtcs; /* Number of CRTCs */
631 int sgx_offset; /* Base offset of SGX device */
632 int hdmi_mask; /* Mask of HDMI CRTCs */
633 int lvds_mask; /* Mask of LVDS CRTCs */
634 int sdvo_mask; /* Mask of SDVO CRTCs */
635 int cursor_needs_phys; /* If cursor base reg need physical address */
636
637 /* Sub functions */
638 struct drm_crtc_helper_funcs const *crtc_helper;
639 struct drm_crtc_funcs const *crtc_funcs;
640 const struct gma_clock_funcs *clock_funcs;
641
642 /* Setup hooks */
643 int (*chip_setup)(struct drm_device *dev);
644 void (*chip_teardown)(struct drm_device *dev);
645 /* Optional helper caller after modeset */
646 void (*errata)(struct drm_device *dev);
647
648 /* Display management hooks */
649 int (*output_init)(struct drm_device *dev);
650 int (*hotplug)(struct drm_device *dev);
651 void (*hotplug_enable)(struct drm_device *dev, bool on);
652 /* Power management hooks */
653 void (*init_pm)(struct drm_device *dev);
654 int (*save_regs)(struct drm_device *dev);
655 int (*restore_regs)(struct drm_device *dev);
656 void (*save_crtc)(struct drm_crtc *crtc);
657 void (*restore_crtc)(struct drm_crtc *crtc);
658 int (*power_up)(struct drm_device *dev);
659 int (*power_down)(struct drm_device *dev);
660 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
661 void (*disable_sr)(struct drm_device *dev);
662
663 void (*lvds_bl_power)(struct drm_device *dev, bool on);
664 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
665 /* Backlight */
666 int (*backlight_init)(struct drm_device *dev);
667 #endif
668 int i2c_bus; /* I2C bus identifier for Moorestown */
669 };
670
671
672
673 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
674 extern int drm_pick_crtcs(struct drm_device *dev);
675
psb_priv(struct drm_device * dev)676 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
677 {
678 return (struct drm_psb_private *) dev->dev_private;
679 }
680
681 /* psb_irq.c */
682 extern irqreturn_t psb_irq_handler(int irq, void *arg);
683 extern int psb_irq_enable_dpst(struct drm_device *dev);
684 extern int psb_irq_disable_dpst(struct drm_device *dev);
685 extern void psb_irq_preinstall(struct drm_device *dev);
686 extern int psb_irq_postinstall(struct drm_device *dev);
687 extern void psb_irq_uninstall(struct drm_device *dev);
688 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
689 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
690
691 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
692 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
693 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
694 extern int psb_enable_vblank(struct drm_device *dev, unsigned int pipe);
695 extern void psb_disable_vblank(struct drm_device *dev, unsigned int pipe);
696 void
697 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
698
699 void
700 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
701
702 extern u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
703
704 /* framebuffer.c */
705 extern int psbfb_probed(struct drm_device *dev);
706 extern int psbfb_remove(struct drm_device *dev,
707 struct drm_framebuffer *fb);
708 /* accel_2d.c */
709 extern void psbfb_copyarea(struct fb_info *info,
710 const struct fb_copyarea *region);
711 extern int psbfb_sync(struct fb_info *info);
712 extern void psb_spank(struct drm_psb_private *dev_priv);
713
714 /* psb_reset.c */
715 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
716 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
717 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
718
719 /* modesetting */
720 extern void psb_modeset_init(struct drm_device *dev);
721 extern void psb_modeset_cleanup(struct drm_device *dev);
722 extern int psb_fbdev_init(struct drm_device *dev);
723
724 /* backlight.c */
725 int gma_backlight_init(struct drm_device *dev);
726 void gma_backlight_exit(struct drm_device *dev);
727 void gma_backlight_disable(struct drm_device *dev);
728 void gma_backlight_enable(struct drm_device *dev);
729 void gma_backlight_set(struct drm_device *dev, int v);
730
731 /* oaktrail_crtc.c */
732 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
733
734 /* oaktrail_lvds.c */
735 extern void oaktrail_lvds_init(struct drm_device *dev,
736 struct psb_intel_mode_device *mode_dev);
737
738 /* psb_intel_display.c */
739 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
740 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
741
742 /* psb_intel_lvds.c */
743 extern const struct drm_connector_helper_funcs
744 psb_intel_lvds_connector_helper_funcs;
745 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
746
747 /* gem.c */
748 extern void psb_gem_free_object(struct drm_gem_object *obj);
749 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
750 struct drm_file *file);
751 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
752 struct drm_mode_create_dumb *args);
753 extern vm_fault_t psb_gem_fault(struct vm_fault *vmf);
754
755 /* psb_device.c */
756 extern const struct psb_ops psb_chip_ops;
757
758 /* oaktrail_device.c */
759 extern const struct psb_ops oaktrail_chip_ops;
760
761 /* mdlfd_device.c */
762 extern const struct psb_ops mdfld_chip_ops;
763
764 /* cdv_device.c */
765 extern const struct psb_ops cdv_chip_ops;
766
767 /* Debug print bits setting */
768 #define PSB_D_GENERAL (1 << 0)
769 #define PSB_D_INIT (1 << 1)
770 #define PSB_D_IRQ (1 << 2)
771 #define PSB_D_ENTRY (1 << 3)
772 /* debug the get H/V BP/FP count */
773 #define PSB_D_HV (1 << 4)
774 #define PSB_D_DBI_BF (1 << 5)
775 #define PSB_D_PM (1 << 6)
776 #define PSB_D_RENDER (1 << 7)
777 #define PSB_D_REG (1 << 8)
778 #define PSB_D_MSVDX (1 << 9)
779 #define PSB_D_TOPAZ (1 << 10)
780
781 extern int drm_idle_check_interval;
782
783 /* Utilities */
MRST_MSG_READ32(int domain,uint port,uint offset)784 static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
785 {
786 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
787 uint32_t ret_val = 0;
788 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
789 pci_write_config_dword(pci_root, 0xD0, mcr);
790 pci_read_config_dword(pci_root, 0xD4, &ret_val);
791 pci_dev_put(pci_root);
792 return ret_val;
793 }
MRST_MSG_WRITE32(int domain,uint port,uint offset,u32 value)794 static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
795 u32 value)
796 {
797 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
798 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
799 pci_write_config_dword(pci_root, 0xD4, value);
800 pci_write_config_dword(pci_root, 0xD0, mcr);
801 pci_dev_put(pci_root);
802 }
MDFLD_MSG_READ32(int domain,uint port,uint offset)803 static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset)
804 {
805 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
806 uint32_t ret_val = 0;
807 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
808 pci_write_config_dword(pci_root, 0xD0, mcr);
809 pci_read_config_dword(pci_root, 0xD4, &ret_val);
810 pci_dev_put(pci_root);
811 return ret_val;
812 }
MDFLD_MSG_WRITE32(int domain,uint port,uint offset,u32 value)813 static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset,
814 u32 value)
815 {
816 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
817 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
818 pci_write_config_dword(pci_root, 0xD4, value);
819 pci_write_config_dword(pci_root, 0xD0, mcr);
820 pci_dev_put(pci_root);
821 }
822
REGISTER_READ(struct drm_device * dev,uint32_t reg)823 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
824 {
825 struct drm_psb_private *dev_priv = dev->dev_private;
826 return ioread32(dev_priv->vdc_reg + reg);
827 }
828
REGISTER_READ_AUX(struct drm_device * dev,uint32_t reg)829 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
830 {
831 struct drm_psb_private *dev_priv = dev->dev_private;
832 return ioread32(dev_priv->aux_reg + reg);
833 }
834
835 #define REG_READ(reg) REGISTER_READ(dev, (reg))
836 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
837
838 /* Useful for post reads */
REGISTER_READ_WITH_AUX(struct drm_device * dev,uint32_t reg,int aux)839 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
840 uint32_t reg, int aux)
841 {
842 uint32_t val;
843
844 if (aux)
845 val = REG_READ_AUX(reg);
846 else
847 val = REG_READ(reg);
848
849 return val;
850 }
851
852 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
853
REGISTER_WRITE(struct drm_device * dev,uint32_t reg,uint32_t val)854 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
855 uint32_t val)
856 {
857 struct drm_psb_private *dev_priv = dev->dev_private;
858 iowrite32((val), dev_priv->vdc_reg + (reg));
859 }
860
REGISTER_WRITE_AUX(struct drm_device * dev,uint32_t reg,uint32_t val)861 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
862 uint32_t val)
863 {
864 struct drm_psb_private *dev_priv = dev->dev_private;
865 iowrite32((val), dev_priv->aux_reg + (reg));
866 }
867
868 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
869 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
870
REGISTER_WRITE_WITH_AUX(struct drm_device * dev,uint32_t reg,uint32_t val,int aux)871 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
872 uint32_t val, int aux)
873 {
874 if (aux)
875 REG_WRITE_AUX(reg, val);
876 else
877 REG_WRITE(reg, val);
878 }
879
880 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
881
REGISTER_WRITE16(struct drm_device * dev,uint32_t reg,uint32_t val)882 static inline void REGISTER_WRITE16(struct drm_device *dev,
883 uint32_t reg, uint32_t val)
884 {
885 struct drm_psb_private *dev_priv = dev->dev_private;
886 iowrite16((val), dev_priv->vdc_reg + (reg));
887 }
888
889 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
890
REGISTER_WRITE8(struct drm_device * dev,uint32_t reg,uint32_t val)891 static inline void REGISTER_WRITE8(struct drm_device *dev,
892 uint32_t reg, uint32_t val)
893 {
894 struct drm_psb_private *dev_priv = dev->dev_private;
895 iowrite8((val), dev_priv->vdc_reg + (reg));
896 }
897
898 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
899
900 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
901 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
902
903 /* #define TRAP_SGX_PM_FAULT 1 */
904 #ifdef TRAP_SGX_PM_FAULT
905 #define PSB_RSGX32(_offs) \
906 ({ \
907 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
908 pr_err("access sgx when it's off!! (READ) %s, %d\n", \
909 __FILE__, __LINE__); \
910 melay(1000); \
911 } \
912 ioread32(dev_priv->sgx_reg + (_offs)); \
913 })
914 #else
915 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
916 #endif
917 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
918
919 #define MSVDX_REG_DUMP 0
920
921 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
922 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
923
924 #endif
925
