Searched refs:rlc_hdr (Results 1 – 5 of 5) sorted by relevance
115 const struct rlc_firmware_header_v1_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local119 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()121 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in amdgpu_ucode_print_rlc_hdr()123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); in amdgpu_ucode_print_rlc_hdr()125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in amdgpu_ucode_print_rlc_hdr()127 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); in amdgpu_ucode_print_rlc_hdr()129 const struct rlc_firmware_header_v2_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local133 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); in amdgpu_ucode_print_rlc_hdr()135 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); in amdgpu_ucode_print_rlc_hdr()[all …]
466 const struct rlc_firmware_header_v2_1 *rlc_hdr; in gfx_v9_0_init_rlc_ext_microcode() local468 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_ext_microcode()469 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()470 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()471 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v9_0_init_rlc_ext_microcode()472 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in gfx_v9_0_init_rlc_ext_microcode()473 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()474 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()475 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v9_0_init_rlc_ext_microcode()476 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in gfx_v9_0_init_rlc_ext_microcode()[all …]
969 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v8_0_init_microcode() local1083 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()1084 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()1085 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()1088 le32_to_cpu(rlc_hdr->save_and_restore_offset); in gfx_v8_0_init_microcode()1090 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); in gfx_v8_0_init_microcode()1092 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); in gfx_v8_0_init_microcode()1094 le32_to_cpu(rlc_hdr->reg_restore_list_size); in gfx_v8_0_init_microcode()1096 le32_to_cpu(rlc_hdr->reg_list_format_start); in gfx_v8_0_init_microcode()1098 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); in gfx_v8_0_init_microcode()[all …]
315 const struct rlc_firmware_header_v1_0 *rlc_hdr; in gfx_v6_0_init_microcode() local376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_init_microcode()377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v6_0_init_microcode()378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
115 const struct rlc_firmware_header_v1_0 *rlc_hdr = in radeon_ucode_print_rlc_hdr() local119 le32_to_cpu(rlc_hdr->ucode_feature_version)); in radeon_ucode_print_rlc_hdr()121 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in radeon_ucode_print_rlc_hdr()123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); in radeon_ucode_print_rlc_hdr()125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in radeon_ucode_print_rlc_hdr()127 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); in radeon_ucode_print_rlc_hdr()
