Home
last modified time | relevance | path

Searched refs:registers (Results 1 – 25 of 1438) sorted by relevance

12345678910>>...58

/Linux-v4.19/sound/soc/ux500/
Dux500_msp_i2s.c144 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
172 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
212 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
214 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
228 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
261 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
267 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
/Linux-v4.19/drivers/media/usb/cpia2/
Dcpia2_core.c256 cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
257 cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
259 cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
260 cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
269 cmd.buffer.registers[0].index = in cpia2_do_command()
271 cmd.buffer.registers[1].index = in cpia2_do_command()
273 cmd.buffer.registers[0].value = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; in cpia2_do_command()
274 cmd.buffer.registers[1].value = in cpia2_do_command()
389 cmd.buffer.registers[0].index = CPIA2_VC_VC_TARGET_KB; in cpia2_do_command()
390 cmd.buffer.registers[0].value = param; in cpia2_do_command()
[all …]
/Linux-v4.19/drivers/media/radio/si470x/
Dradio-si470x-common.c194 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
195 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
212 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
218 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
219 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
231 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
238 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
251 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
274 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
336 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
Dradio-si470x-i2c.c107 radio->registers[regnr] = __be16_to_cpu(buf[READ_INDEX(regnr)]); in si470x_get_register()
129 buf[i] = __cpu_to_be16(radio->registers[WRITE_INDEX(i)]); in si470x_set_register()
163 radio->registers[i] = __be16_to_cpu(buf[READ_INDEX(i)]); in si470x_get_all_registers()
192 radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN; in si470x_fops_open()
193 radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN; in si470x_fops_open()
194 radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2; in si470x_fops_open()
195 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
265 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_i2c_interrupt()
269 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0) in si470x_i2c_interrupt()
280 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) in si470x_i2c_interrupt()
[all …]
Dradio-si470x-usb.c262 radio->registers[regnr] = get_unaligned_be16(&radio->usb_buf[1]); in si470x_get_register()
276 put_unaligned_be16(radio->registers[regnr], &radio->usb_buf[1]); in si470x_set_register()
303 radio->registers[regnr] = get_unaligned_be16( in si470x_get_all_registers()
397 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
400 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_int_in_callback()
403 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS)) { in si470x_int_in_callback()
406 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
410 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) { in si470x_int_in_callback()
414 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSS) == 0) { in si470x_int_in_callback()
421 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
[all …]
/Linux-v4.19/drivers/scsi/smartpqi/
Dsmartpqi_sis.c96 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
102 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
137 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
147 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
154 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
166 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
172 registers = ctrl_info->registers; in sis_send_sync_cmd()
175 writel(cmd, &registers->sis_mailbox[0]); in sis_send_sync_cmd()
182 writel(params->mailbox[i], &registers->sis_mailbox[i]); in sis_send_sync_cmd()
186 &registers->sis_ctrl_to_host_doorbell_clear); in sis_send_sync_cmd()
[all …]
/Linux-v4.19/drivers/gpio/
Dgpio-74x164.c26 u32 registers; member
40 chip->registers); in __gen_74x164_write_config()
46 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value()
61 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value()
82 for (i = 0, bank = chip->registers - 1; i < chip->registers; in gen_74x164_set_multiple()
146 chip->registers = nregs; in gen_74x164_probe()
147 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
/Linux-v4.19/drivers/char/agp/
Damd-k7-agp.c32 volatile u8 __iomem *registers; member
216 if (!amd_irongate_private.registers) { in amd_irongate_configure()
219 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in amd_irongate_configure()
220 if (!amd_irongate_private.registers) in amd_irongate_configure()
225 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); in amd_irongate_configure()
226 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
238 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ in amd_irongate_configure()
246 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
[all …]
Dsworks-agp.c39 volatile u8 __iomem *registers; member
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
275 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); in serverworks_configure()
276 if (!serverworks_private.registers) { in serverworks_configure()
281 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
282 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ in serverworks_configure()
284 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); in serverworks_configure()
[all …]
Dintel-gtt.c66 u8 __iomem *registers; member
186 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
187 if (!intel_private.registers) in i810_setup()
191 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
195 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
207 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
363 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
436 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
438 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
441 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/net/
Dbrcm,amac.txt9 contains the information of registers in the same order as
11 - reg-names: Names of the registers.
12 "amac_base": Address and length of the GMAC registers
13 "idm_base": Address and length of the GMAC IDM registers
16 registers (required for Northstar2)
/Linux-v4.19/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the OHCI registers location and length
117 - reg : should contain the EHCI registers location and length
127 - reg : should contain the SDHCI registers location and length
136 - reg : should contain the IPC registers location and length
[all …]
Dgamecube.txt22 - reg : should contain the VI registers location and length
33 - reg : should contain the PI registers location and length
53 - reg : should contain the DSP registers location and length
74 - reg : should contain the DI registers location and length
85 - reg : should contain the AI registers location and length
97 - reg : should contain the SI registers location and length
107 - reg : should contain the EXI registers location and length
/Linux-v4.19/Documentation/devicetree/bindings/mips/
Dmscc.txt14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
20 - reg : Should contain registers location and length
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
37 - reg : Should contain registers location and length
/Linux-v4.19/Documentation/sh/
Dregister-banks.txt14 In the case of this type of banking, banked registers are mapped directly to
16 can still be used to reference the banked registers (as r0_bank ... r7_bank)
18 in mind when writing code that utilizes these banked registers, for obvious
20 be used rather effectively as scratch registers by the kernel.
22 Presently the kernel uses several of these registers.
25 registers when doing exception handling).
/Linux-v4.19/Documentation/devicetree/bindings/arm/marvell/
Dcoherency-fabric.txt18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
/Linux-v4.19/Documentation/devicetree/bindings/auxdisplay/
Dimg-ascii-lcd.txt10 - reg : memory region locating the device registers
13 - regmap: phandle of the system controller containing the LCD registers
14 - offset: offset in bytes to the LCD registers within the system controller
16 The layout of the registers & properties of the display are determined
/Linux-v4.19/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt15 - ranges: ranges describing the MMIO registers to control the PCIe
21 The ranges describing the MMIO registers have the following layout:
28 registers of this PCIe interface, from the base of the internal
29 registers.
32 registers area. This range entry translates the '0x82000000 0 r' PCI
62 - assigned-addresses: reference to the MMIO registers used to control
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,armada-370-xp-mpic.txt12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
14 interrupt registers. For this last pair, to be compliant with SMP
15 support, the "virtual" must be use (For the record, these registers
16 automatically map to the interrupt controller registers of the
/Linux-v4.19/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
65 - reg : <registers mapping>
83 - dcr-reg : <DCR registers range>
/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c418 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) in adreno_gpu_state_get()
419 count += adreno_gpu->registers[i + 1] - in adreno_gpu_state_get()
420 adreno_gpu->registers[i] + 1; in adreno_gpu_state_get()
422 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); in adreno_gpu_state_get()
423 if (state->registers) { in adreno_gpu_state_get()
426 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { in adreno_gpu_state_get()
427 u32 start = adreno_gpu->registers[i]; in adreno_gpu_state_get()
428 u32 end = adreno_gpu->registers[i + 1]; in adreno_gpu_state_get()
432 state->registers[pos++] = addr; in adreno_gpu_state_get()
433 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/arm/
Dversatile-sysreg.txt1 ARM Versatile system registers
4 This is a system control registers block, providing multiple low level
10 - reg : physical base address and the size of the registers window
/Linux-v4.19/Documentation/devicetree/bindings/arm/amlogic/
Dassist.txt1 Amlogic Meson6/Meson8/Meson8b assist registers:
4 The assist registers contain basic information about the SoC,
8 - reg: the register range of the assist registers
/Linux-v4.19/Documentation/devicetree/bindings/mfd/
Dsyscon.txt4 of miscellaneous registers. The registers are not cohesive enough to
9 OS driver) to determine the location of the registers, and access the
10 registers directly.
/Linux-v4.19/drivers/usb/storage/
Dshuttle_usbat.c513 unsigned char *registers, in usbat_hp8200e_rw_block_test() argument
590 data[j<<1] = registers[j]; in usbat_hp8200e_rw_block_test()
677 unsigned char *registers, in usbat_multiple_write() argument
708 data[i<<1] = registers[i]; in usbat_multiple_write()
1053 unsigned char registers[3] = { in usbat_flash_get_sector_count() local
1071 rc = usbat_multiple_write(us, registers, command, 3); in usbat_flash_get_sector_count()
1111 unsigned char registers[7] = { in usbat_flash_read_data() local
1167 result = usbat_multiple_write(us, registers, command, 7); in usbat_flash_read_data()
1202 unsigned char registers[7] = { in usbat_flash_write_data() local
1262 result = usbat_multiple_write(us, registers, command, 7); in usbat_flash_write_data()
[all …]

12345678910>>...58