Searched refs:reg_tbl (Results 1 – 14 of 14) sorted by relevance
40 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))44 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
531 u32 *reg_tbl; member
265 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_83xx_register_map()3609 sizeof(*adapter->ahw->reg_tbl)); in qlcnic_83xx_get_regs_len()
662 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_sriov_vf_register_map()
2498 ahw->reg_tbl = (u32 *) qlcnic_reg_tbl; in qlcnic_probe()
411 .reg_tbl = msm8916_reg_preset,440 .reg_tbl = msm8996_reg_preset,
42 const struct reg_val *reg_tbl; member
375 const struct reg_val *tbl = res->reg_tbl; in venus_set_registers()
809 uint32_t *reg_tbl; member1049 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); in qla4_8xxx_rd_direct()1056 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); in qla4_8xxx_wr_direct()
454 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]); in qla4_83xx_can_perform_reset()456 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]); in qla4_83xx_can_perform_reset()
8638 ha->reg_tbl = (uint32_t *) qla4_82xx_reg_tbl; in qla4xxx_probe_adapter()8650 ha->reg_tbl = (uint32_t *)qla4_83xx_reg_tbl; in qla4xxx_probe_adapter()
2209 } reg_tbl[] = { in bnx2x_test_registers() local2321 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { in bnx2x_test_registers()2323 if (!(hw & reg_tbl[i].hw)) in bnx2x_test_registers()2326 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; in bnx2x_test_registers()2327 mask = reg_tbl[i].mask; in bnx2x_test_registers()
5580 } reg_tbl[] = { in bnx2_test_registers() local5694 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in bnx2_test_registers()5696 u16 flags = reg_tbl[i].flags; in bnx2_test_registers()5701 offset = (u32) reg_tbl[i].offset; in bnx2_test_registers()5702 rw_mask = reg_tbl[i].rw_mask; in bnx2_test_registers()5703 ro_mask = reg_tbl[i].ro_mask; in bnx2_test_registers()
13111 } reg_tbl[] = { in tg3_test_registers() local13254 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in tg3_test_registers()13255 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) in tg3_test_registers()13258 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) in tg3_test_registers()13262 (reg_tbl[i].flags & TG3_FL_NOT_5788)) in tg3_test_registers()13265 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) in tg3_test_registers()13268 offset = (u32) reg_tbl[i].offset; in tg3_test_registers()13269 read_mask = reg_tbl[i].read_mask; in tg3_test_registers()13270 write_mask = reg_tbl[i].write_mask; in tg3_test_registers()
