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Searched refs:reg_offset (Results 1 – 25 of 214) sorted by relevance

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/Linux-v4.19/drivers/mfd/
Dsec-irq.c29 .reg_offset = 0,
33 .reg_offset = 0,
37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 0,
57 .reg_offset = 0,
61 .reg_offset = 1,
65 .reg_offset = 1,
[all …]
Dda9052-irq.c40 .reg_offset = 0,
44 .reg_offset = 0,
48 .reg_offset = 0,
52 .reg_offset = 0,
56 .reg_offset = 0,
60 .reg_offset = 0,
64 .reg_offset = 0,
68 .reg_offset = 0,
72 .reg_offset = 1,
76 .reg_offset = 1,
[all …]
Dwm5110-tables.c313 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
314 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
315 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
316 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
319 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
322 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
325 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
328 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
334 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
[all …]
Dtps65910.c61 .reg_offset = 0,
65 .reg_offset = 0,
69 .reg_offset = 0,
73 .reg_offset = 0,
77 .reg_offset = 0,
81 .reg_offset = 0,
85 .reg_offset = 0,
89 .reg_offset = 0,
95 .reg_offset = 1,
99 .reg_offset = 1,
[all …]
Dpalmas.c78 .reg_offset = 1,
82 .reg_offset = 1,
86 .reg_offset = 1,
90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
106 .reg_offset = 1,
111 .reg_offset = 2,
115 .reg_offset = 2,
[all …]
Drk808.c191 .reg_offset = 0,
195 .reg_offset = 0,
199 .reg_offset = 0,
203 .reg_offset = 0,
207 .reg_offset = 0,
211 .reg_offset = 0,
215 .reg_offset = 0,
219 .reg_offset = 0,
227 .reg_offset = 0,
231 .reg_offset = 0,
[all …]
Dcs47l24-tables.c39 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
40 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
43 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
46 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
49 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
52 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
55 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
58 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
61 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
64 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
[all …]
Dmax8907.c119 { .reg_offset = 0, .mask = 1 << 0, },
120 { .reg_offset = 0, .mask = 1 << 1, },
121 { .reg_offset = 0, .mask = 1 << 2, },
122 { .reg_offset = 1, .mask = 1 << 0, },
123 { .reg_offset = 1, .mask = 1 << 1, },
124 { .reg_offset = 1, .mask = 1 << 2, },
125 { .reg_offset = 1, .mask = 1 << 3, },
126 { .reg_offset = 1, .mask = 1 << 4, },
127 { .reg_offset = 1, .mask = 1 << 5, },
128 { .reg_offset = 1, .mask = 1 << 6, },
[all …]
Dwm8994-irq.c33 .reg_offset = 1,
37 .reg_offset = 1,
41 .reg_offset = 1,
45 .reg_offset = 1,
49 .reg_offset = 1,
53 .reg_offset = 1,
57 .reg_offset = 1,
61 .reg_offset = 1,
65 .reg_offset = 1,
69 .reg_offset = 1,
[all …]
Dmax14577.c203 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
204 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
205 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
207 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
208 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
209 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
210 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
211 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
213 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
214 { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
[all …]
Das3722.c112 .reg_offset = 1,
116 .reg_offset = 1,
120 .reg_offset = 1,
124 .reg_offset = 1,
128 .reg_offset = 1,
132 .reg_offset = 1,
136 .reg_offset = 1,
140 .reg_offset = 1,
146 .reg_offset = 2,
150 .reg_offset = 2,
[all …]
Dwm8998-tables.c79 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
80 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
81 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
82 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
85 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
88 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
91 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
94 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
97 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
100 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
[all …]
Dwm5102-tables.c127 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
128 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
129 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
130 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
133 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
136 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
139 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
143 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
146 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
149 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
[all …]
Dwm8997-tables.c63 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
64 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
65 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
66 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
69 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
72 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
75 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
78 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
81 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
84 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
[all …]
Dda9150-core.c262 .reg_offset = 0,
266 .reg_offset = 0,
270 .reg_offset = 0,
274 .reg_offset = 0,
278 .reg_offset = 0,
282 .reg_offset = 1,
286 .reg_offset = 1,
290 .reg_offset = 1,
294 .reg_offset = 1,
298 .reg_offset = 1,
[all …]
Dmax77693.c130 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
131 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
132 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
133 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
135 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
136 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
137 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
138 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
139 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
140 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
[all …]
Dda9062-core.c36 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
40 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
44 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
49 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
53 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
57 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
61 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
66 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
70 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
74 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
[all …]
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dvega10_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
44 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
[all …]
Dvega20_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
44 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
[all …]
Dmmsch_v1_0.h51 uint32_t reg_offset : 28; member
56 uint32_t reg_offset : 20; member
89 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
92 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
102 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
111 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
114 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
Dsoc15_common.h28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
31 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
32 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
36 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
39 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
42 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
48 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
52 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
56 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
/Linux-v4.19/drivers/soc/zte/
Dzx296718_pm_domains.c40 .reg_offset = zx296718_offsets,
49 .reg_offset = zx296718_offsets,
58 .reg_offset = zx296718_offsets,
67 .reg_offset = zx296718_offsets,
76 .reg_offset = zx296718_offsets,
85 .reg_offset = zx296718_offsets,
94 .reg_offset = zx296718_offsets,
103 .reg_offset = zx296718_offsets,
112 .reg_offset = zx296718_offsets,
121 .reg_offset = zx296718_offsets,
[all …]
/Linux-v4.19/drivers/phy/rockchip/
Dphy-rockchip-emmc.c87 unsigned int reg_offset; member
106 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
111 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
164 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
177 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, in rockchip_emmc_phy_power()
187 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power()
193 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
225 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, in rockchip_emmc_phy_power()
286 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power_on()
293 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power_on()
[all …]
/Linux-v4.19/drivers/gpio/
Dgpio-madera.c32 unsigned int reg_offset = 2 * offset; in madera_gpio_get_direction() local
36 ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_2 + reg_offset, in madera_gpio_get_direction()
48 unsigned int reg_offset = 2 * offset; in madera_gpio_direction_in() local
51 MADERA_GPIO1_CTRL_2 + reg_offset, in madera_gpio_direction_in()
59 unsigned int reg_offset = 2 * offset; in madera_gpio_get() local
63 ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_1 + reg_offset, in madera_gpio_get()
76 unsigned int reg_offset = 2 * offset; in madera_gpio_direction_out() local
81 MADERA_GPIO1_CTRL_2 + reg_offset, in madera_gpio_direction_out()
87 MADERA_GPIO1_CTRL_1 + reg_offset, in madera_gpio_direction_out()
96 unsigned int reg_offset = 2 * offset; in madera_gpio_set() local
[all …]
/Linux-v4.19/drivers/gpu/drm/gma500/
Dintel_gmbus.c253 int i, reg_offset; in gmbus_xfer() local
259 reg_offset = 0; in gmbus_xfer()
261 GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0); in gmbus_xfer()
268 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
274 GMBUS_REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
278 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & in gmbus_xfer()
281 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) in gmbus_xfer()
284 val = GMBUS_REG_READ(GMBUS3 + reg_offset); in gmbus_xfer()
298 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
299 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
[all …]

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