Searched refs:reference_divider (Results 1 – 14 of 14) sorted by relevance
53 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local62 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()97 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value()132 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local140 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()173 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value()
133 u32 reference_divider; in rv740_populate_sclk_value() local142 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()165 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value()
325 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local334 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()337 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()502 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local511 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()518 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()544 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value()
2011 u32 reference_divider; in ni_calculate_sclk_params() local2020 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()2023 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()2044 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params()
4794 u32 reference_divider; in si_calculate_sclk_params() local4803 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()4805 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()4826 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
3168 u32 reference_divider; in ci_calculate_sclk_params() local3178 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()3191 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()
227 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()327 if (pll_settings->reference_divider) { in calculate_pixel_clock_pll_dividers()328 min_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()329 max_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()442 pll_settings->reference_divider = in pll_adjust_pix_clk()443 bp_adjust_pixel_clock_params.reference_divider; in pll_adjust_pix_clk()759 pll_settings->reference_divider * ss_data->modulation_freq_hz); in calculate_ss()949 bp_pc_params.reference_divider = pll_settings->reference_divider; in dce110_program_pix_clk()
199 uint32_t reference_divider; member216 uint32_t reference_divider; member
112 uint32_t reference_divider; member
959 cpu_to_le16((uint16_t)bp_params->reference_divider); in set_pixel_clock_v3()1030 (uint8_t)(bp_params->reference_divider); in set_pixel_clock_v5()1106 (uint8_t) bp_params->reference_divider; in set_pixel_clock_v6()1523 bp_params->reference_divider = params.sOutput.ucRefDiv; in adjust_display_pll_v3()
806 uint32_t reference_divider; in iceland_calculate_sclk_params() local819 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()849 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in iceland_calculate_sclk_params()
539 uint32_t reference_divider; in tonga_calculate_sclk_params() local552 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()582 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in tonga_calculate_sclk_params()
5258 u32 reference_divider; in si_calculate_sclk_params() local5267 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()5269 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()5290 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
3314 u32 reference_divider; in ci_calculate_sclk_params() local3324 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()3337 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()
