Searched refs:read_aux_reg (Results 1 – 18 of 18) sorted by relevance
480 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()489 unsigned int val = read_aux_reg(ctl); in __before_dc_op()517 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) in __after_dc_op()553 write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS); in __dc_disable()560 write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS); in __dc_enable()601 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ in __ic_entire_inv()678 ctrl = read_aux_reg(ARC_REG_SLC_CTRL); in slc_op_rgn()710 read_aux_reg(ARC_REG_SLC_CTRL); in slc_op_rgn()712 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); in slc_op_rgn()737 ctrl = read_aux_reg(ARC_REG_SLC_CTRL); in slc_op_line()[all …]
133 idx = read_aux_reg(ARC_REG_TLBINDEX); in tlb_entry_lkup()181 idx = read_aux_reg(ARC_REG_TLBINDEX); in utlb_invalidate()565 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff; in create_tlb()762 tmp = read_aux_reg(ARC_REG_MMU_BCR); in read_decode_mmu_bcr()930 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()993 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff; in tlb_paranoid_check()
15 #define read_aux_reg(r) __builtin_arc_lr(r) macro22 static inline int read_aux_reg(u32 r) in read_aux_reg() function41 tmp = read_aux_reg(reg); \
81 l = read_aux_reg(ARC_REG_MCIP_READBACK); in arc_read_gfrc()84 h = read_aux_reg(ARC_REG_MCIP_READBACK); in arc_read_gfrc()134 l = read_aux_reg(AUX_RTC_LOW); in arc_read_rtc()135 h = read_aux_reg(AUX_RTC_HIGH); in arc_read_rtc()136 status = read_aux_reg(AUX_RTC_CTRL); in arc_read_rtc()185 return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); in arc_read_timer1()
144 enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); in nps_clkevent_rm_thread()147 thread = read_aux_reg(CTOP_AUX_THREAD_ID); in nps_clkevent_rm_thread()169 thread = read_aux_reg(CTOP_AUX_THREAD_ID); in nps_clkevent_add_thread()170 enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); in nps_clkevent_add_thread()
95 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_read_counter()97 result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32; in arc_pmu_read_counter()98 result |= read_aux_reg(ARC_REG_PCT_SNAPL); in arc_pmu_read_counter()204 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_enable()212 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_disable()280 read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx)); in arc_pmu_start()300 read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~(1 << idx)); in arc_pmu_stop()382 active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT); in arc_pmu_intr()403 read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx)); in arc_pmu_intr()493 cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); in arc_pmu_device_probe()[all …]
51 ienb = read_aux_reg(AUX_IENABLE); in arc_init_IRQ()72 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_mask()81 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_unmask()
88 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); in read_decode_ccm_bcr()102 region = read_aux_reg(ARC_REG_AUX_ICCM); in read_decode_ccm_bcr()112 region = read_aux_reg(ARC_REG_AUX_DCCM); in read_decode_ccm_bcr()148 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); in read_arc_build_cfg_regs()152 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ in read_arc_build_cfg_regs()153 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ in read_arc_build_cfg_regs()154 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ in read_arc_build_cfg_regs()155 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; in read_arc_build_cfg_regs()156 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ in read_arc_build_cfg_regs()309 ctl = read_aux_reg(ARC_REG_LPB_CTRL); in arc_cpu_mumbojumbo()
47 gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_update_gfrc_halt_mask()67 mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_update_debug_halt_mask()120 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_ipi_send()142 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ in mcip_ipi_clear()
95 tmp = read_aux_reg(ARC_REG_STATUS32); in arc_init_IRQ()
27 prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS); in dp_save_restore()30 prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1); in dp_save_restore()
73 hw_comply.value = read_aux_reg(CTOP_AUX_HW_COMPLY); in eznps_init_core()
54 udmc.value = read_aux_reg(CTOP_AUX_UDMC); in mtm_init_nat()
61 ienb = read_aux_reg(AUX_IENABLE); in nps400_irq_mask()71 ienb = read_aux_reg(AUX_IENABLE); in nps400_irq_unmask()
77 unsigned int irqact = read_aux_reg(AUX_IRQ_ACT); in arch_local_irq_enable()
360 pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \
63 #define read_aux_reg(r) 0 macro
322 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; in axs103_early_init()
