Home
last modified time | relevance | path

Searched refs:rd (Results 1 – 25 of 456) sorted by relevance

12345678910>>...19

/Linux-v4.19/arch/arm/include/debug/
Dsamsung.S12 .macro fifo_level_s5pv210 rd, rx
13 ldr \rd, [\rx, # S3C2410_UFSTAT]
14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
18 .macro fifo_full_s5pv210 rd, rx
19 ldr \rd, [\rx, # S3C2410_UFSTAT]
20 ARM_BE8(rev \rd, \rd)
21 tst \rd, #S5PV210_UFSTAT_TXFULL
27 .macro fifo_level_s3c2440 rd, rx
28 ldr \rd, [\rx, # S3C2410_UFSTAT]
[all …]
D8250.S18 .macro store, rd, rx:vararg
19 ARM_BE8(rev \rd, \rd)
20 str \rd, \rx
21 ARM_BE8(rev \rd, \rd)
24 .macro load, rd, rx:vararg
25 ldr \rd, \rx
26 ARM_BE8(rev \rd, \rd)
29 .macro store, rd, rx:vararg
30 strb \rd, \rx
33 .macro load, rd, rx:vararg
[all …]
Dmsm.S23 .macro senduart, rd, rx
24 ARM_BE8(rev \rd, \rd )
26 str \rd, [\rx, #0x70]
29 .macro waituart, rd, rx
31 ldr \rd, [\rx, #0x08]
32 ARM_BE8(rev \rd, \rd )
33 tst \rd, #0x08
36 1001: ldr \rd, [\rx, #0x14]
37 ARM_BE8(rev \rd, \rd )
38 tst \rd, #0x80
[all …]
Dicedcc.S19 .macro senduart, rd, rx
20 mcr p14, 0, \rd, c0, c5, 0
23 .macro busyuart, rd, rx
30 .macro waituart, rd, rx
31 mov \rd, #0x2000000
33 subs \rd, \rd, #1
43 .macro senduart, rd, rx
44 mcr p14, 0, \rd, c8, c0, 0
47 .macro busyuart, rd, rx
54 .macro waituart, rd, rx
[all …]
Dpl01x.S29 .macro senduart,rd,rx
30 strb \rd, [\rx, #UART01x_DR]
33 .macro waituart,rd,rx
34 1001: ldr \rd, [\rx, #UART01x_FR]
35 ARM_BE8( rev \rd, \rd )
36 tst \rd, #UART01x_FR_TXFF
40 .macro busyuart,rd,rx
41 1001: ldr \rd, [\rx, #UART01x_FR]
42 ARM_BE8( rev \rd, \rd )
43 tst \rd, #UART01x_FR_BUSY
Drenesas-scif.S32 .macro waituart, rd, rx
33 1001: ldrh \rd, [\rx, #FSR]
34 tst \rd, #TDFE
38 .macro senduart, rd, rx
39 strb \rd, [\rx, #FTDR]
40 ldrh \rd, [\rx, #FSR]
41 bic \rd, \rd, #TEND
42 strh \rd, [\rx, #FSR]
45 .macro busyuart, rd, rx
46 1001: ldrh \rd, [\rx, #FSR]
[all …]
Dzynq.S40 .macro senduart,rd,rx
41 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
44 .macro waituart,rd,rx
45 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
46 ARM_BE8( rev \rd, \rd )
47 tst \rd, #UART_SR_TXEMPTY
51 .macro busyuart,rd,rx
52 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
53 ARM_BE8( rev \rd, \rd )
54 tst \rd, #UART_SR_TXFULL @
Domap2plus.S67 .macro senduart,rd,rx
68 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
70 strb \rd, [\rx] @ send lower byte of rd
71 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
72 bic \rd, \rd, #(0xff << 24) @ restore original rd
75 .macro busyuart,rd,rx
76 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
77 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
78 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
82 .macro waituart,rd,rx
Dimx.S37 .macro senduart,rd,rx
38 ARM_BE8(rev \rd, \rd)
39 str \rd, [\rx, #0x40] @ TXDATA
42 .macro waituart,rd,rx
45 .macro busyuart,rd,rx
46 1002: ldr \rd, [\rx, #0x98] @ SR2
47 ARM_BE8(rev \rd, \rd)
48 tst \rd, #1 << 3 @ TXDC
/Linux-v4.19/arch/arm/net/
Dbpf_jit_32.h161 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
163 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
167 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
168 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
169 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
170 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
171 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
172 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
174 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
175 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) argument
[all …]
Dbpf_jit_32.c417 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i_no8m() argument
420 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); in emit_mov_i_no8m()
422 emit(ARM_MOVW(rd, val & 0xffff), ctx); in emit_mov_i_no8m()
424 emit(ARM_MOVT(rd, val >> 16), ctx); in emit_mov_i_no8m()
428 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i() argument
433 emit(ARM_MOV_I(rd, imm12), ctx); in emit_mov_i()
435 emit_mov_i_no8m(rd, val, ctx); in emit_mov_i()
468 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op) in emit_udivmod() argument
475 emit(ARM_UDIV(rd, rm, rn), ctx); in emit_udivmod()
478 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); in emit_udivmod()
[all …]
/Linux-v4.19/drivers/gpu/drm/msm/
Dmsm_rd.c109 static void rd_write(struct msm_rd_state *rd, const void *buf, int sz) in rd_write() argument
111 struct circ_buf *fifo = &rd->fifo; in rd_write()
118 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0); in rd_write()
124 n = min(sz, circ_space_to_end(&rd->fifo)); in rd_write()
131 wake_up_all(&rd->fifo_event); in rd_write()
135 static void rd_write_section(struct msm_rd_state *rd, in rd_write_section() argument
138 rd_write(rd, &type, 4); in rd_write_section()
139 rd_write(rd, &sz, 4); in rd_write_section()
140 rd_write(rd, buf, sz); in rd_write_section()
146 struct msm_rd_state *rd = file->private_data; in rd_read() local
[all …]
/Linux-v4.19/drivers/powercap/
Dintel_rapl.c206 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
242 static int rapl_read_data_raw(struct rapl_domain *rd,
245 static int rapl_write_data_raw(struct rapl_domain *rd,
248 static u64 rapl_unit_xlate(struct rapl_domain *rd,
281 struct rapl_domain *rd; in get_energy_counter() local
288 rd = power_zone_to_rapl_domain(power_zone); in get_energy_counter()
290 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { in get_energy_counter()
303 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); in get_max_energy_counter() local
305 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); in get_max_energy_counter()
311 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); in release_zone() local
[all …]
/Linux-v4.19/kernel/time/
Dsched_clock.c101 struct clock_read_data *rd; in sched_clock() local
105 rd = cd.read_data + (seq & 1); in sched_clock()
107 cyc = (rd->read_sched_clock() - rd->epoch_cyc) & in sched_clock()
108 rd->sched_clock_mask; in sched_clock()
109 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock()
125 static void update_clock_read_data(struct clock_read_data *rd) in update_clock_read_data() argument
128 cd.read_data[1] = *rd; in update_clock_read_data()
134 cd.read_data[0] = *rd; in update_clock_read_data()
147 struct clock_read_data rd; in update_sched_clock() local
149 rd = cd.read_data[0]; in update_sched_clock()
[all …]
/Linux-v4.19/fs/jffs2/
Dwrite.c206 struct jffs2_raw_dirent *rd, const unsigned char *name, in jffs2_write_dirent() argument
218 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
219 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent()
221 D1(if(je32_to_cpu(rd->hdr_crc) != crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)) { in jffs2_write_dirent()
231 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
232 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent()
237 vecs[0].iov_base = rd; in jffs2_write_dirent()
238 vecs[0].iov_len = sizeof(*rd); in jffs2_write_dirent()
246 fd->version = je32_to_cpu(rd->version); in jffs2_write_dirent()
247 fd->ino = je32_to_cpu(rd->ino); in jffs2_write_dirent()
[all …]
Ddir.c285 struct jffs2_raw_dirent *rd; in jffs2_symlink() local
379 ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &alloclen, in jffs2_symlink()
384 rd = jffs2_alloc_raw_dirent(); in jffs2_symlink()
385 if (!rd) { in jffs2_symlink()
395 rd->magic = cpu_to_je16(JFFS2_MAGIC_BITMASK); in jffs2_symlink()
396 rd->nodetype = cpu_to_je16(JFFS2_NODETYPE_DIRENT); in jffs2_symlink()
397 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_symlink()
398 rd->hdr_crc = cpu_to_je32(crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)); in jffs2_symlink()
400 rd->pino = cpu_to_je32(dir_i->i_ino); in jffs2_symlink()
401 rd->version = cpu_to_je32(++dir_f->highest_version); in jffs2_symlink()
[all …]
/Linux-v4.19/arch/sparc/include/asm/
Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
59 b getcc_trap_handler; rd %psr, %l0; nop; nop;
63 b setcc_trap_handler; rd %psr, %l0; nop; nop;
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
[all …]
/Linux-v4.19/drivers/media/tuners/
Dqt1010.c60 qt1010_i2c_oper_t rd[48] = { in qt1010_set_params() local
132 rd[2].val = reg05; in qt1010_set_params()
135 rd[4].val = (freq + QT1010_OFFSET) / FREQ1; in qt1010_set_params()
138 if (mod1 < 8000000) rd[6].val = 0x1d; in qt1010_set_params()
139 else rd[6].val = 0x1c; in qt1010_set_params()
142 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
143 else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */ in qt1010_set_params()
144 else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */ in qt1010_set_params()
145 else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */ in qt1010_set_params()
146 else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */ in qt1010_set_params()
[all …]
/Linux-v4.19/drivers/reset/
Dreset-pistachio.c69 struct pistachio_reset_data *rd; in pistachio_reset_assert() local
73 rd = container_of(rcdev, struct pistachio_reset_data, rcdev); in pistachio_reset_assert()
79 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
86 struct pistachio_reset_data *rd; in pistachio_reset_deassert() local
90 rd = container_of(rcdev, struct pistachio_reset_data, rcdev); in pistachio_reset_deassert()
96 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_deassert()
107 struct pistachio_reset_data *rd; in pistachio_reset_probe() local
111 rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL); in pistachio_reset_probe()
112 if (!rd) in pistachio_reset_probe()
115 rd->periph_regs = syscon_node_to_regmap(np->parent); in pistachio_reset_probe()
[all …]
/Linux-v4.19/arch/unicore32/mm/
Dproc-macros.S41 .macro vma_vm_mm, rd, rn
42 ldw \rd, [\rn+], #VMA_VM_MM
48 .macro vma_vm_flags, rd, rn
49 ldw \rd, [\rn+], #VMA_VM_FLAGS
52 .macro tsk_mm, rd, rn
53 ldw \rd, [\rn+], #TI_TASK
54 ldw \rd, [\rd+], #TSK_ACTIVE_MM
60 .macro act_mm, rd
61 andn \rd, sp, #8128
62 andn \rd, \rd, #63
[all …]
/Linux-v4.19/arch/arm/mach-tegra/
Dsleep.h62 .macro cpu_to_halt_reg rd, rcpu
64 subne \rd, \rcpu, #1
65 movne \rd, \rd, lsl #3
66 addne \rd, \rd, #0x14
67 moveq \rd, #0
71 .macro cpu_to_csr_reg rd, rcpu
73 subne \rd, \rcpu, #1
74 movne \rd, \rd, lsl #3
75 addne \rd, \rd, #0x18
76 moveq \rd, #8
[all …]
/Linux-v4.19/arch/unicore32/kernel/
Ddebug-macro.S17 .macro put_word_ocd, rd, rx=r16
21 movc p1.c1, \rd, #1
29 .macro senduart, rd, rx
30 put_word_ocd \rd, \rx
33 .macro busyuart, rd, rx
36 .macro waituart, rd, rx
73 .macro senduart,rd,rx
74 str \rd, [\rx, #UART_THR_OFFSET]
77 .macro waituart,rd,rx
78 1001: ldr \rd, [\rx, #UART_LSR_OFFSET]
[all …]
/Linux-v4.19/arch/arm/lib/
Dio-writesb.S13 .macro outword, rd
15 strb \rd, [r0]
16 mov \rd, \rd, lsr #8
17 strb \rd, [r0]
18 mov \rd, \rd, lsr #8
19 strb \rd, [r0]
20 mov \rd, \rd, lsr #8
21 strb \rd, [r0]
23 mov lr, \rd, lsr #24
25 mov lr, \rd, lsr #16
[all …]
/Linux-v4.19/drivers/clk/samsung/
Dclk-exynos5-subcmu.c20 struct exynos5_subcmu_reg_dump *rd, in exynos5_subcmu_clk_save() argument
23 for (; num_regs > 0; --num_regs, ++rd) { in exynos5_subcmu_clk_save()
24 rd->save = readl(base + rd->offset); in exynos5_subcmu_clk_save()
25 writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); in exynos5_subcmu_clk_save()
26 rd->save &= rd->mask; in exynos5_subcmu_clk_save()
31 struct exynos5_subcmu_reg_dump *rd, in exynos5_subcmu_clk_restore() argument
34 for (; num_regs > 0; --num_regs, ++rd) in exynos5_subcmu_clk_restore()
35 writel((readl(base + rd->offset) & ~rd->mask) | rd->save, in exynos5_subcmu_clk_restore()
36 base + rd->offset); in exynos5_subcmu_clk_restore()
/Linux-v4.19/drivers/media/dvb-frontends/
Ddib3000mb.c346 rd(DIB3000MB_REG_AS_IRQ_PENDING), in dib3000mb_set_frontend()
347 rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100) in dib3000mb_set_frontend()
454 if (!rd(DIB3000MB_REG_TPS_LOCK)) in dib3000mb_get_frontend()
457 dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB); in dib3000mb_get_frontend()
458 …deb_getf("DDS_VAL: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VAL… in dib3000mb_get_frontend()
466 dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB); in dib3000mb_get_frontend()
467 …deb_getf("DDS_FREQ: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FRE… in dib3000mb_get_frontend()
482 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) { in dib3000mb_get_frontend()
501 if (rd(DIB3000MB_REG_TPS_HRCH)) { in dib3000mb_get_frontend()
505 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) { in dib3000mb_get_frontend()
[all …]

12345678910>>...19