Searched refs:rFPGA0_XA_HSSIParameter1 (Results 1 – 10 of 10) sorted by relevance
11 #define rFPGA0_XA_HSSIParameter1 0x820 macro
624 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
605 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl88e_phy_init_bb_rf_register_definition()
84 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8)); in rf_serial_read()890 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); in pi_mode_switch()1014 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, in phy_iq_calibrate()
61 #define rFPGA0_XA_HSSIParameter1 0x820 macro
429 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in _rtl92e_init_bb_rf_reg_def()
93 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
102 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
68 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
168 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
