Searched refs:rFPGA0_IQK (Results 1 – 4 of 4) sorted by relevance
| /Linux-v4.19/drivers/staging/rtl8723bs/hal/ |
| D | HalPhyRf_8723B.c | 446 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); in phy_PathA_IQK_8723B()
478 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); in phy_PathA_IQK_8723B()
507 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); in phy_PathA_IQK_8723B()
557 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); in phy_PathA_RxIQK8723B()
569 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); in phy_PathA_RxIQK8723B()
592 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); in phy_PathA_RxIQK8723B()
621 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); in phy_PathA_RxIQK8723B()
660 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); in phy_PathA_RxIQK8723B()
693 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); in phy_PathA_RxIQK8723B()
722 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); in phy_PathA_RxIQK8723B()
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| /Linux-v4.19/drivers/staging/rtl8188eu/hal/ |
| D | phy.c | 584 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); in phy_path_a_rx_iqk()
594 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); in phy_path_a_rx_iqk()
635 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); in phy_path_a_rx_iqk()
640 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); in phy_path_a_rx_iqk()
666 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); in phy_path_a_rx_iqk()
880 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x0); in path_a_standby()
882 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); in path_a_standby()
1052 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); in phy_iq_calibrate()
1119 phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0); in phy_iq_calibrate()
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| /Linux-v4.19/drivers/staging/rtl8723bs/include/ |
| D | Hal8192CPhyReg.h | 309 #define rFPGA0_IQK 0xe28 macro
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| /Linux-v4.19/drivers/staging/rtl8188eu/include/ |
| D | hal8188e_phy_reg.h | 285 #define rFPGA0_IQK 0xe28 macro
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