Searched refs:r17 (Results 1 – 25 of 122) sorted by relevance
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124 shr.u r17=r16,61 // get the region number into r17137 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?140 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place149 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5150 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]158 ld8 r17=[r17] // get *pgd (may be 0)160 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?162 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)168 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)170 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)[all …]
61 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \68 cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \85 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \88 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \91 lfetch.fault.excl.nt1 [r17]; \97 adds r17=PT(R9),r1; /* initialize second base pointer */ \101 .mem.offset 8,0; st8.spill [r17]=r9,16; \104 .mem.offset 8,0; st8.spill [r17]=r11,24; \107 st8 [r17]=r30,16; /* save cr.ifs */ \115 st8 [r17]=r26,16; /* save ar.pfs */ \[all …]
124 ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF) // get pointer to signal handler's plabel138 ld8 r10=[r17],8 // get signal handler entry point141 ld8 gp=[r17] // get signal handler's global pointer249 ld8 r17=[r16]253 mov ar.rsc=r17 // put RSE into enforced lazy mode254 shr.u r17=r17,16256 sub r14=r14,r17 // r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)257 shr.u r17=r17,3 // r17 <- (sc_loadrs >> 19)262 add r14=r14,r17 // r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)266 sub r14=r14,r17 // r14 <- -rse_num_regs(bspstore1, bsp1)[all …]
65 add r17=IA64_TASK_SIGNAL_OFFSET,r1667 ld8 r17=[r17] // r17 = current->signal71 add r17=IA64_SIGNAL_PIDS_TGID_OFFSET,r1774 ld8 r17=[r17] // r17 = current->signal->pids[PIDTYPE_TGID]76 add r8=IA64_PID_LEVEL_OFFSET,r1779 add r17=IA64_PID_UPID_OFFSET,r17 // r17 = &pid->numbers[0]83 add r17=r17,r8 // r17 = &pid->numbers[pid->level]85 ld4 r8=[r17] // r8 = pid->numbers[pid->level].nr87 mov r17=099 add r17=IA64_TASK_THREAD_PID_OFFSET,r16[all …]
240 movl r17=KERNEL_START243 mov cr.ifa=r17267 movl r17=1f269 mov cr.iip=r17279 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)321 movl r17=PAGE_KERNEL326 or r18=r17,r18329 mov r17=rr[r2]332 dep r17=0,r17,8,24334 mov cr.itir=r17[all …]
65 addl r17=O(PTCE_STRIDE),r270 ld4 r21=[r17],4 // r21=ptce_stride[0]73 ld4 r22=[r17] // r22=ptce_stride[1]170 movl r17=KERNEL_START173 mov cr.ifa=r17178 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT180 or r18=r17,r18316 mov r22=r17 // *minstate485 st8 [temp1]=r17,16 // pal_min_state626 add r1=32*1,r17[all …]
246 .save @priunat,r17247 mov r17=ar.unat // preserve caller's347 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat390 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc443 mov ar.lc=r17472 adds r17=PT(F7)+16,sp475 stf.spill [r17]=f7,32478 stf.spill [r17]=f9,32481 stf.spill [r17]=f11489 adds r17=PT(F7)+16,sp[all …]
66 addl r17=O(PTCE_STRIDE),r271 ld4 r21=[r17],4 // r21=ptce_stride[0]74 ld4 r22=[r17] // r22=ptce_stride[1]139 (p6) and r17=r30, r16159 st8 [r17]=r14;;160 fc.i r17161 add r17=8, r17266 st8 [in0]=r17, 8 // r17
77 movl r17=PSR_BITS_TO_SET79 or loc3=loc3,r17
60 movl r17=PSR_BITS_TO_SET62 or loc3=loc3,r17
175 movl r17=PAL_PSR_BITS_TO_SET177 or loc3=loc3,r17 // add in psr the bits to set227 movl r17=PAL_PSR_BITS_TO_SET229 or loc3=loc3,r17 // add in psr the bits to set
48 l.or r17, r5, r0 // Set r17 = n60 l.addi r17, r17, -1 // Decrease n68 l.addi r17, r17, -1 // Decrease n76 l.addi r17, r17, -1 // Decrease n81 l.addi r17, r17, -4 // Decrease n82 l.sfgeui r17, 487 l.sfeqi r17, 091 3: l.addi r17, r17, -1 // Decrease n93 l.sfnei r17, 0
27 stm.w (r17 - r19, lr), [sp-]28 mov r17, r034 stm.w (r0 - r15), [r17]+38 ldm.w (r17 - r19, pc), [sp]+
213 u8 r12, r15, r17, r18, r3D, r82, r84, r89; in mxl111sf_config_pin_mux_modes() local218 ret = mxl111sf_read_reg(state, 0x17, &r17); in mxl111sf_config_pin_mux_modes()246 r17 |= PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()274 r17 |= PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()302 r17 &= ~PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()330 r17 &= ~PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()358 r17 &= ~PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()386 r17 &= ~PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()414 r17 &= ~PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()442 r17 &= ~PIN_MUX_MPEG_MODE_MASK; in mxl111sf_config_pin_mux_modes()[all …]
36 mov r17 = in245 (p[0]) ld8.nta s2[0] = [r17], 874 mov r17 = in284 (p[0]) ld8.nta s2[0] = [r17], 8115 mov r17 = in2126 (p[0]) ld8.nta s2[0] = [r17], 8159 mov r17 = in2171 (p[0]) ld8.nta s2[0] = [r17], 8
15 std r17, 136(%r1)55 li r17, 0x171756 std r17, -192(%r1)115 cmpwi r17, 0x1717159 li r17, 0xde209 ld r17, -192(%r1)210 cmpwi r17, 0x1717255 ld r17, 136(%r1)
35 movi $r17, -152 slti $r17, $r16, #453 bnez $r17, 1f54 addi $r17, $r19, #-255 mtsr $r17, $PSW
119 mov r17=0x3ffff /* implemented PMD */128 st8 [r29]=r17,16 /* store implemented PMD */134 mov r17=0xf0 /* retired bundles capable PMC */142 st8 [r29]=r17,16 /* store retired bundle capable */
116 std r17,STK_REG(R17)(r1)133 ld r17,96(r4)150 std r17,96(r3)160 ld r17,STK_REG(R17)(r1)
30 std r17,(top_pos - 112)(%r1); \50 ld r17,(top_pos - 112)(%r1); \77 ld r17,24(r3)
144 stw r17, 68(sp)269 movi r17, 0281 xor r17, r3, r5 /* MSB contains sign of quotient */352 bge r17, zero, quotient_is_nonnegative575 ldw r17, 68(sp)
130 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ argument149 .radio_txmix5g_boost_tune_core0 = r17, \162 r10, r11, r12, r13, r14, r15, r16, r17) \ argument180 .radio_lna2g_tune_core1 = r17
46 mr %r17,%r3 /* save cpu id to r17 */65 STWX_BE %r17,%r3,%r4 /* Store my cpu as __be32 at byte 28 */
44 lmw1 $r17, $r1, $r2446 smw1 $r17, $r0, $r24
34 unsigned long r17; member93 PTREGS_INFO(r17), \
