1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #ifndef _HW_H_
20 #define _HW_H_
21
22 #include "targaddrs.h"
23
24 #define ATH10K_FW_DIR "ath10k"
25
26 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
27 #define QCA988X_2_0_DEVICE_ID (0x003c)
28 #define QCA6164_2_1_DEVICE_ID (0x0041)
29 #define QCA6174_2_1_DEVICE_ID (0x003e)
30 #define QCA99X0_2_0_DEVICE_ID (0x0040)
31 #define QCA9888_2_0_DEVICE_ID (0x0056)
32 #define QCA9984_1_0_DEVICE_ID (0x0046)
33 #define QCA9377_1_0_DEVICE_ID (0x0042)
34 #define QCA9887_1_0_DEVICE_ID (0x0050)
35
36 /* QCA988X 1.0 definitions (unsupported) */
37 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
38
39 /* QCA988X 2.0 definitions */
40 #define QCA988X_HW_2_0_VERSION 0x4100016c
41 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
42 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
43 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
44 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
45
46 /* QCA9887 1.0 definitions */
47 #define QCA9887_HW_1_0_VERSION 0x4100016d
48 #define QCA9887_HW_1_0_CHIP_ID_REV 0
49 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0"
50 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin"
51 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234
52
53 /* QCA6174 target BMI version signatures */
54 #define QCA6174_HW_1_0_VERSION 0x05000000
55 #define QCA6174_HW_1_1_VERSION 0x05000001
56 #define QCA6174_HW_1_3_VERSION 0x05000003
57 #define QCA6174_HW_2_1_VERSION 0x05010000
58 #define QCA6174_HW_3_0_VERSION 0x05020000
59 #define QCA6174_HW_3_2_VERSION 0x05030000
60
61 /* QCA9377 target BMI version signatures */
62 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000
63 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001
64
65 enum qca6174_pci_rev {
66 QCA6174_PCI_REV_1_1 = 0x11,
67 QCA6174_PCI_REV_1_3 = 0x13,
68 QCA6174_PCI_REV_2_0 = 0x20,
69 QCA6174_PCI_REV_3_0 = 0x30,
70 };
71
72 enum qca6174_chip_id_rev {
73 QCA6174_HW_1_0_CHIP_ID_REV = 0,
74 QCA6174_HW_1_1_CHIP_ID_REV = 1,
75 QCA6174_HW_1_3_CHIP_ID_REV = 2,
76 QCA6174_HW_2_1_CHIP_ID_REV = 4,
77 QCA6174_HW_2_2_CHIP_ID_REV = 5,
78 QCA6174_HW_3_0_CHIP_ID_REV = 8,
79 QCA6174_HW_3_1_CHIP_ID_REV = 9,
80 QCA6174_HW_3_2_CHIP_ID_REV = 10,
81 };
82
83 enum qca9377_chip_id_rev {
84 QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
85 QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
86 };
87
88 #define QCA6174_HW_2_1_FW_DIR ATH10K_FW_DIR "/QCA6174/hw2.1"
89 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin"
90 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
91
92 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0"
93 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin"
94 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
95
96 /* QCA99X0 1.0 definitions (unsupported) */
97 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0
98
99 /* QCA99X0 2.0 definitions */
100 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000
101 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1
102 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0"
103 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
104 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
105
106 /* QCA9984 1.0 defines */
107 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000
108 #define QCA9984_HW_DEV_TYPE 0xa
109 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0
110 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0"
111 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
112 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234
113
114 /* QCA9888 2.0 defines */
115 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000
116 #define QCA9888_HW_DEV_TYPE 0xc
117 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0
118 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0"
119 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin"
120 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234
121
122 /* QCA9377 1.0 definitions */
123 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
124 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
125 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234
126
127 /* QCA4019 1.0 definitions */
128 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000
129 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0"
130 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
131 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234
132
133 /* WCN3990 1.0 definitions */
134 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990
135 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0"
136
137 #define ATH10K_FW_FILE_BASE "firmware"
138 #define ATH10K_FW_API_MAX 6
139 #define ATH10K_FW_API_MIN 2
140
141 #define ATH10K_FW_API2_FILE "firmware-2.bin"
142 #define ATH10K_FW_API3_FILE "firmware-3.bin"
143
144 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
145 #define ATH10K_FW_API4_FILE "firmware-4.bin"
146
147 /* HTT id conflict fix for management frames over HTT */
148 #define ATH10K_FW_API5_FILE "firmware-5.bin"
149
150 /* the firmware-6.bin blob */
151 #define ATH10K_FW_API6_FILE "firmware-6.bin"
152
153 #define ATH10K_FW_UTF_FILE "utf.bin"
154 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin"
155
156 /* includes also the null byte */
157 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
158 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD"
159
160 #define ATH10K_BOARD_API2_FILE "board-2.bin"
161
162 #define REG_DUMP_COUNT_QCA988X 60
163
164 struct ath10k_fw_ie {
165 __le32 id;
166 __le32 len;
167 u8 data[0];
168 };
169
170 enum ath10k_fw_ie_type {
171 ATH10K_FW_IE_FW_VERSION = 0,
172 ATH10K_FW_IE_TIMESTAMP = 1,
173 ATH10K_FW_IE_FEATURES = 2,
174 ATH10K_FW_IE_FW_IMAGE = 3,
175 ATH10K_FW_IE_OTP_IMAGE = 4,
176
177 /* WMI "operations" interface version, 32 bit value. Supported from
178 * FW API 4 and above.
179 */
180 ATH10K_FW_IE_WMI_OP_VERSION = 5,
181
182 /* HTT "operations" interface version, 32 bit value. Supported from
183 * FW API 5 and above.
184 */
185 ATH10K_FW_IE_HTT_OP_VERSION = 6,
186
187 /* Code swap image for firmware binary */
188 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
189 };
190
191 enum ath10k_fw_wmi_op_version {
192 ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
193
194 ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
195 ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
196 ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
197 ATH10K_FW_WMI_OP_VERSION_TLV = 4,
198 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
199 ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
200
201 /* keep last */
202 ATH10K_FW_WMI_OP_VERSION_MAX,
203 };
204
205 enum ath10k_fw_htt_op_version {
206 ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
207
208 ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
209
210 /* also used in 10.2 and 10.2.4 branches */
211 ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
212
213 ATH10K_FW_HTT_OP_VERSION_TLV = 3,
214
215 ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
216
217 /* keep last */
218 ATH10K_FW_HTT_OP_VERSION_MAX,
219 };
220
221 enum ath10k_bd_ie_type {
222 /* contains sub IEs of enum ath10k_bd_ie_board_type */
223 ATH10K_BD_IE_BOARD = 0,
224 };
225
226 enum ath10k_bd_ie_board_type {
227 ATH10K_BD_IE_BOARD_NAME = 0,
228 ATH10K_BD_IE_BOARD_DATA = 1,
229 };
230
231 enum ath10k_hw_rev {
232 ATH10K_HW_QCA988X,
233 ATH10K_HW_QCA6174,
234 ATH10K_HW_QCA99X0,
235 ATH10K_HW_QCA9888,
236 ATH10K_HW_QCA9984,
237 ATH10K_HW_QCA9377,
238 ATH10K_HW_QCA4019,
239 ATH10K_HW_QCA9887,
240 ATH10K_HW_WCN3990,
241 };
242
243 struct ath10k_hw_regs {
244 u32 rtc_soc_base_address;
245 u32 rtc_wmac_base_address;
246 u32 soc_core_base_address;
247 u32 wlan_mac_base_address;
248 u32 ce_wrapper_base_address;
249 u32 ce0_base_address;
250 u32 ce1_base_address;
251 u32 ce2_base_address;
252 u32 ce3_base_address;
253 u32 ce4_base_address;
254 u32 ce5_base_address;
255 u32 ce6_base_address;
256 u32 ce7_base_address;
257 u32 ce8_base_address;
258 u32 ce9_base_address;
259 u32 ce10_base_address;
260 u32 ce11_base_address;
261 u32 soc_reset_control_si0_rst_mask;
262 u32 soc_reset_control_ce_rst_mask;
263 u32 soc_chip_id_address;
264 u32 scratch_3_address;
265 u32 fw_indicator_address;
266 u32 pcie_local_base_address;
267 u32 ce_wrap_intr_sum_host_msi_lsb;
268 u32 ce_wrap_intr_sum_host_msi_mask;
269 u32 pcie_intr_fw_mask;
270 u32 pcie_intr_ce_mask_all;
271 u32 pcie_intr_clr_address;
272 u32 cpu_pll_init_address;
273 u32 cpu_speed_address;
274 u32 core_clk_div_address;
275 };
276
277 extern const struct ath10k_hw_regs qca988x_regs;
278 extern const struct ath10k_hw_regs qca6174_regs;
279 extern const struct ath10k_hw_regs qca99x0_regs;
280 extern const struct ath10k_hw_regs qca4019_regs;
281 extern const struct ath10k_hw_regs wcn3990_regs;
282
283 struct ath10k_hw_ce_regs_addr_map {
284 u32 msb;
285 u32 lsb;
286 u32 mask;
287 };
288
289 struct ath10k_hw_ce_ctrl1 {
290 u32 addr;
291 u32 hw_mask;
292 u32 sw_mask;
293 u32 hw_wr_mask;
294 u32 sw_wr_mask;
295 u32 reset_mask;
296 u32 reset;
297 struct ath10k_hw_ce_regs_addr_map *src_ring;
298 struct ath10k_hw_ce_regs_addr_map *dst_ring;
299 struct ath10k_hw_ce_regs_addr_map *dmax; };
300
301 struct ath10k_hw_ce_cmd_halt {
302 u32 status_reset;
303 u32 msb;
304 u32 mask;
305 struct ath10k_hw_ce_regs_addr_map *status; };
306
307 struct ath10k_hw_ce_host_ie {
308 u32 copy_complete_reset;
309 struct ath10k_hw_ce_regs_addr_map *copy_complete; };
310
311 struct ath10k_hw_ce_host_wm_regs {
312 u32 dstr_lmask;
313 u32 dstr_hmask;
314 u32 srcr_lmask;
315 u32 srcr_hmask;
316 u32 cc_mask;
317 u32 wm_mask;
318 u32 addr;
319 };
320
321 struct ath10k_hw_ce_misc_regs {
322 u32 axi_err;
323 u32 dstr_add_err;
324 u32 srcr_len_err;
325 u32 dstr_mlen_vio;
326 u32 dstr_overflow;
327 u32 srcr_overflow;
328 u32 err_mask;
329 u32 addr;
330 };
331
332 struct ath10k_hw_ce_dst_src_wm_regs {
333 u32 addr;
334 u32 low_rst;
335 u32 high_rst;
336 struct ath10k_hw_ce_regs_addr_map *wm_low;
337 struct ath10k_hw_ce_regs_addr_map *wm_high; };
338
339 struct ath10k_hw_ce_ctrl1_upd {
340 u32 shift;
341 u32 mask;
342 u32 enable;
343 };
344
345 struct ath10k_hw_ce_regs {
346 u32 sr_base_addr;
347 u32 sr_size_addr;
348 u32 dr_base_addr;
349 u32 dr_size_addr;
350 u32 ce_cmd_addr;
351 u32 misc_ie_addr;
352 u32 sr_wr_index_addr;
353 u32 dst_wr_index_addr;
354 u32 current_srri_addr;
355 u32 current_drri_addr;
356 u32 ddr_addr_for_rri_low;
357 u32 ddr_addr_for_rri_high;
358 u32 ce_rri_low;
359 u32 ce_rri_high;
360 u32 host_ie_addr;
361 struct ath10k_hw_ce_host_wm_regs *wm_regs;
362 struct ath10k_hw_ce_misc_regs *misc_regs;
363 struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
364 struct ath10k_hw_ce_cmd_halt *cmd_halt;
365 struct ath10k_hw_ce_host_ie *host_ie;
366 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
367 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
368 struct ath10k_hw_ce_ctrl1_upd *upd;
369 };
370
371 struct ath10k_hw_values {
372 u32 rtc_state_val_on;
373 u8 ce_count;
374 u8 msi_assign_ce_max;
375 u8 num_target_ce_config_wlan;
376 u16 ce_desc_meta_data_mask;
377 u8 ce_desc_meta_data_lsb;
378 };
379
380 extern const struct ath10k_hw_values qca988x_values;
381 extern const struct ath10k_hw_values qca6174_values;
382 extern const struct ath10k_hw_values qca99x0_values;
383 extern const struct ath10k_hw_values qca9888_values;
384 extern const struct ath10k_hw_values qca4019_values;
385 extern const struct ath10k_hw_values wcn3990_values;
386 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs;
387 extern const struct ath10k_hw_ce_regs qcax_ce_regs;
388
389 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
390 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
391
392 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
393 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
394 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
395 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
396 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
397 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
398 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
399 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
400 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
401
402 /* Known peculiarities:
403 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
404 * - raw have FCS, nwifi doesn't
405 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
406 * param, llc/snap) are aligned to 4byte boundaries each
407 */
408 enum ath10k_hw_txrx_mode {
409 ATH10K_HW_TXRX_RAW = 0,
410
411 /* Native Wifi decap mode is used to align IP frames to 4-byte
412 * boundaries and avoid a very expensive re-alignment in mac80211.
413 */
414 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
415 ATH10K_HW_TXRX_ETHERNET = 2,
416
417 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
418 ATH10K_HW_TXRX_MGMT = 3,
419 };
420
421 enum ath10k_mcast2ucast_mode {
422 ATH10K_MCAST2UCAST_DISABLED = 0,
423 ATH10K_MCAST2UCAST_ENABLED = 1,
424 };
425
426 enum ath10k_hw_rate_ofdm {
427 ATH10K_HW_RATE_OFDM_48M = 0,
428 ATH10K_HW_RATE_OFDM_24M,
429 ATH10K_HW_RATE_OFDM_12M,
430 ATH10K_HW_RATE_OFDM_6M,
431 ATH10K_HW_RATE_OFDM_54M,
432 ATH10K_HW_RATE_OFDM_36M,
433 ATH10K_HW_RATE_OFDM_18M,
434 ATH10K_HW_RATE_OFDM_9M,
435 };
436
437 enum ath10k_hw_rate_cck {
438 ATH10K_HW_RATE_CCK_LP_11M = 0,
439 ATH10K_HW_RATE_CCK_LP_5_5M,
440 ATH10K_HW_RATE_CCK_LP_2M,
441 ATH10K_HW_RATE_CCK_LP_1M,
442 ATH10K_HW_RATE_CCK_SP_11M,
443 ATH10K_HW_RATE_CCK_SP_5_5M,
444 ATH10K_HW_RATE_CCK_SP_2M,
445 };
446
447 enum ath10k_hw_rate_rev2_cck {
448 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
449 ATH10K_HW_RATE_REV2_CCK_LP_2M,
450 ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
451 ATH10K_HW_RATE_REV2_CCK_LP_11M,
452 ATH10K_HW_RATE_REV2_CCK_SP_2M,
453 ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
454 ATH10K_HW_RATE_REV2_CCK_SP_11M,
455 };
456
457 enum ath10k_hw_cc_wraparound_type {
458 ATH10K_HW_CC_WRAP_DISABLED = 0,
459
460 /* This type is when the HW chip has a quirky Cycle Counter
461 * wraparound which resets to 0x7fffffff instead of 0. All
462 * other CC related counters (e.g. Rx Clear Count) are divided
463 * by 2 so they never wraparound themselves.
464 */
465 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
466
467 /* Each hw counter wrapsaround independently. When the
468 * counter overflows the repestive counter is right shifted
469 * by 1, i.e reset to 0x7fffffff, and other counters will be
470 * running unaffected. In this type of wraparound, it should
471 * be possible to report accurate Rx busy time unlike the
472 * first type.
473 */
474 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
475 };
476
477 enum ath10k_hw_refclk_speed {
478 ATH10K_HW_REFCLK_UNKNOWN = -1,
479 ATH10K_HW_REFCLK_48_MHZ = 0,
480 ATH10K_HW_REFCLK_19_2_MHZ = 1,
481 ATH10K_HW_REFCLK_24_MHZ = 2,
482 ATH10K_HW_REFCLK_26_MHZ = 3,
483 ATH10K_HW_REFCLK_37_4_MHZ = 4,
484 ATH10K_HW_REFCLK_38_4_MHZ = 5,
485 ATH10K_HW_REFCLK_40_MHZ = 6,
486 ATH10K_HW_REFCLK_52_MHZ = 7,
487
488 /* must be the last one */
489 ATH10K_HW_REFCLK_COUNT,
490 };
491
492 struct ath10k_hw_clk_params {
493 u32 refclk;
494 u32 div;
495 u32 rnfrac;
496 u32 settle_time;
497 u32 refdiv;
498 u32 outdiv;
499 };
500
501 struct ath10k_hw_params {
502 u32 id;
503 u16 dev_id;
504 const char *name;
505 u32 patch_load_addr;
506 int uart_pin;
507 u32 otp_exe_param;
508
509 /* Type of hw cycle counter wraparound logic, for more info
510 * refer enum ath10k_hw_cc_wraparound_type.
511 */
512 enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
513
514 /* Some of chip expects fragment descriptor to be continuous
515 * memory for any TX operation. Set continuous_frag_desc flag
516 * for the hardware which have such requirement.
517 */
518 bool continuous_frag_desc;
519
520 /* CCK hardware rate table mapping for the newer chipsets
521 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
522 * are in a proper order with respect to the rate/preamble
523 */
524 bool cck_rate_map_rev2;
525
526 u32 channel_counters_freq_hz;
527
528 /* Mgmt tx descriptors threshold for limiting probe response
529 * frames.
530 */
531 u32 max_probe_resp_desc_thres;
532
533 u32 tx_chain_mask;
534 u32 rx_chain_mask;
535 u32 max_spatial_stream;
536 u32 cal_data_len;
537
538 struct ath10k_hw_params_fw {
539 const char *dir;
540 const char *board;
541 size_t board_size;
542 size_t board_ext_size;
543 } fw;
544
545 /* qca99x0 family chips deliver broadcast/multicast management
546 * frames encrypted and expect software do decryption.
547 */
548 bool sw_decrypt_mcast_mgmt;
549
550 const struct ath10k_hw_ops *hw_ops;
551
552 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */
553 int decap_align_bytes;
554
555 /* hw specific clock control parameters */
556 const struct ath10k_hw_clk_params *hw_clk;
557 int target_cpu_freq;
558
559 /* Number of bytes to be discarded for each FFT sample */
560 int spectral_bin_discard;
561
562 /* The board may have a restricted NSS for 160 or 80+80 vs what it
563 * can do for 80Mhz.
564 */
565 int vht160_mcs_rx_highest;
566 int vht160_mcs_tx_highest;
567
568 /* Number of ciphers supported (i.e First N) in cipher_suites array */
569 int n_cipher_suites;
570
571 u32 num_peers;
572 u32 ast_skid_limit;
573 u32 num_wds_entries;
574
575 /* Targets supporting physical addressing capability above 32-bits */
576 bool target_64bit;
577
578 /* Target rx ring fill level */
579 u32 rx_ring_fill_level;
580
581 /* target supporting per ce IRQ */
582 bool per_ce_irq;
583
584 /* target supporting shadow register for ce write */
585 bool shadow_reg_support;
586
587 /* target supporting retention restore on ddr */
588 bool rri_on_ddr;
589
590 /* Number of bytes to be the offset for each FFT sample */
591 int spectral_bin_offset;
592 };
593
594 struct htt_rx_desc;
595
596 /* Defines needed for Rx descriptor abstraction */
597 struct ath10k_hw_ops {
598 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
599 void (*set_coverage_class)(struct ath10k *ar, s16 value);
600 int (*enable_pll_clk)(struct ath10k *ar);
601 };
602
603 extern const struct ath10k_hw_ops qca988x_ops;
604 extern const struct ath10k_hw_ops qca99x0_ops;
605 extern const struct ath10k_hw_ops qca6174_ops;
606 extern const struct ath10k_hw_ops wcn3990_ops;
607
608 extern const struct ath10k_hw_clk_params qca6174_clk[];
609
610 static inline int
ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)611 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
612 struct htt_rx_desc *rxd)
613 {
614 if (hw->hw_ops->rx_desc_get_l3_pad_bytes)
615 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd);
616 return 0;
617 }
618
619 /* Target specific defines for MAIN firmware */
620 #define TARGET_NUM_VDEVS 8
621 #define TARGET_NUM_PEER_AST 2
622 #define TARGET_NUM_WDS_ENTRIES 32
623 #define TARGET_DMA_BURST_SIZE 0
624 #define TARGET_MAC_AGGR_DELIM 0
625 #define TARGET_AST_SKID_LIMIT 16
626 #define TARGET_NUM_STATIONS 16
627 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
628 (TARGET_NUM_VDEVS))
629 #define TARGET_NUM_OFFLOAD_PEERS 0
630 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
631 #define TARGET_NUM_PEER_KEYS 2
632 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
633 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
634 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
635 #define TARGET_RX_TIMEOUT_LO_PRI 100
636 #define TARGET_RX_TIMEOUT_HI_PRI 40
637
638 #define TARGET_SCAN_MAX_PENDING_REQS 4
639 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
640 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
641 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
642 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
643 #define TARGET_NUM_MCAST_GROUPS 0
644 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
645 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
646 #define TARGET_TX_DBG_LOG_SIZE 1024
647 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
648 #define TARGET_VOW_CONFIG 0
649 #define TARGET_NUM_MSDU_DESC (1024 + 400)
650 #define TARGET_MAX_FRAG_ENTRIES 0
651
652 /* Target specific defines for 10.X firmware */
653 #define TARGET_10X_NUM_VDEVS 16
654 #define TARGET_10X_NUM_PEER_AST 2
655 #define TARGET_10X_NUM_WDS_ENTRIES 32
656 #define TARGET_10X_DMA_BURST_SIZE 0
657 #define TARGET_10X_MAC_AGGR_DELIM 0
658 #define TARGET_10X_AST_SKID_LIMIT 128
659 #define TARGET_10X_NUM_STATIONS 128
660 #define TARGET_10X_TX_STATS_NUM_STATIONS 118
661 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
662 (TARGET_10X_NUM_VDEVS))
663 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \
664 (TARGET_10X_NUM_VDEVS))
665 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
666 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
667 #define TARGET_10X_NUM_PEER_KEYS 2
668 #define TARGET_10X_NUM_TIDS_MAX 256
669 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
670 (TARGET_10X_NUM_PEERS) * 2)
671 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
672 (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
673 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
674 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
675 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
676 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
677 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
678 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
679 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
680 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
681 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
682 #define TARGET_10X_NUM_MCAST_GROUPS 0
683 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
684 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
685 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
686 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
687 #define TARGET_10X_VOW_CONFIG 0
688 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
689 #define TARGET_10X_MAX_FRAG_ENTRIES 0
690
691 /* 10.2 parameters */
692 #define TARGET_10_2_DMA_BURST_SIZE 0
693
694 /* Target specific defines for WMI-TLV firmware */
695 #define TARGET_TLV_NUM_VDEVS 4
696 #define TARGET_TLV_NUM_STATIONS 32
697 #define TARGET_TLV_NUM_PEERS 33
698 #define TARGET_TLV_NUM_TDLS_VDEVS 1
699 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
700 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
701 #define TARGET_TLV_NUM_WOW_PATTERNS 22
702 #define TARGET_TLV_MGMT_NUM_MSDU_DESC (50)
703
704 /* Target specific defines for WMI-HL-1.0 firmware */
705 #define TARGET_HL_10_TLV_NUM_PEERS 14
706 #define TARGET_HL_10_TLV_AST_SKID_LIMIT 6
707 #define TARGET_HL_10_TLV_NUM_WDS_ENTRIES 2
708
709 /* Diagnostic Window */
710 #define CE_DIAG_PIPE 7
711
712 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
713
714 /* Target specific defines for 10.4 firmware */
715 #define TARGET_10_4_NUM_VDEVS 16
716 #define TARGET_10_4_NUM_STATIONS 32
717 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \
718 (TARGET_10_4_NUM_VDEVS))
719 #define TARGET_10_4_ACTIVE_PEERS 0
720
721 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512
722 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50
723 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35
724 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0
725 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0
726 #define TARGET_10_4_NUM_PEER_KEYS 2
727 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2)
728 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400)
729 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500
730 #define TARGET_10_4_AST_SKID_LIMIT 32
731
732 /* 100 ms for video, best-effort, and background */
733 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100
734
735 /* 40 ms for voice */
736 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40
737
738 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
739 #define TARGET_10_4_SCAN_MAX_REQS 4
740 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3
741 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3
742 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8
743
744 /* Note: mcast to ucast is disabled by default */
745 #define TARGET_10_4_NUM_MCAST_GROUPS 0
746 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0
747 #define TARGET_10_4_MCAST2UCAST_MODE 0
748
749 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024
750 #define TARGET_10_4_NUM_WDS_ENTRIES 32
751 #define TARGET_10_4_DMA_BURST_SIZE 0
752 #define TARGET_10_4_MAC_AGGR_DELIM 0
753 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
754 #define TARGET_10_4_VOW_CONFIG 0
755 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3
756 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2
757 #define TARGET_10_4_MAX_PEER_EXT_STATS 16
758 #define TARGET_10_4_SMART_ANT_CAP 0
759 #define TARGET_10_4_BK_MIN_FREE 0
760 #define TARGET_10_4_BE_MIN_FREE 0
761 #define TARGET_10_4_VI_MIN_FREE 0
762 #define TARGET_10_4_VO_MIN_FREE 0
763 #define TARGET_10_4_RX_BATCH_MODE 1
764 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0
765 #define TARGET_10_4_ATF_CONFIG 0
766 #define TARGET_10_4_IPHDR_PAD_CONFIG 1
767 #define TARGET_10_4_QWRAP_CONFIG 0
768
769 /* TDLS config */
770 #define TARGET_10_4_NUM_TDLS_VDEVS 1
771 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1
772 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1
773
774 /* Maximum number of Copy Engine's supported */
775 #define CE_COUNT_MAX 12
776
777 /* Number of Copy Engines supported */
778 #define CE_COUNT ar->hw_values->ce_count
779
780 /*
781 * Granted MSIs are assigned as follows:
782 * Firmware uses the first
783 * Remaining MSIs, if any, are used by Copy Engines
784 * This mapping is known to both Target firmware and Host software.
785 * It may be changed as long as Host and Target are kept in sync.
786 */
787 /* MSI for firmware (errors, etc.) */
788 #define MSI_ASSIGN_FW 0
789
790 /* MSIs for Copy Engines */
791 #define MSI_ASSIGN_CE_INITIAL 1
792 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max
793
794 /* as of IP3.7.1 */
795 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on
796
797 #define RTC_STATE_V_LSB 0
798 #define RTC_STATE_V_MASK 0x00000007
799 #define RTC_STATE_ADDRESS 0x0000
800 #define PCIE_SOC_WAKE_V_MASK 0x00000001
801 #define PCIE_SOC_WAKE_ADDRESS 0x0004
802 #define PCIE_SOC_WAKE_RESET 0x00000000
803 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
804
805 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
806 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
807 #define MAC_COEX_BASE_ADDRESS 0x00006000
808 #define BT_COEX_BASE_ADDRESS 0x00007000
809 #define SOC_PCIE_BASE_ADDRESS 0x00008000
810 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
811 #define WLAN_UART_BASE_ADDRESS 0x0000c000
812 #define WLAN_SI_BASE_ADDRESS 0x00010000
813 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
814 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
815 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address
816 #define EFUSE_BASE_ADDRESS 0x00030000
817 #define FPGA_REG_BASE_ADDRESS 0x00039000
818 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
819 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
820 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address
821 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address
822 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address
823 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address
824 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address
825 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address
826 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address
827 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address
828 #define DBI_BASE_ADDRESS 0x00060000
829 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
830 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address
831
832 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
833 #define SOC_RESET_CONTROL_OFFSET 0x00000000
834 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
835 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
836 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
837 #define SOC_CPU_CLOCK_OFFSET 0x00000020
838 #define SOC_CPU_CLOCK_STANDARD_LSB 0
839 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
840 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
841 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
842 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
843 #define SOC_LPO_CAL_OFFSET 0x000000e0
844 #define SOC_LPO_CAL_ENABLE_LSB 20
845 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
846 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
847 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
848
849 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
850 #define SOC_CHIP_ID_REV_LSB 8
851 #define SOC_CHIP_ID_REV_MASK 0x00000f00
852
853 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
854 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
855 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
856 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
857
858 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
859 #define WLAN_GPIO_PIN0_CONFIG_LSB 11
860 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
861 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5
862 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060
863 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
864 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
865 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
866 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
867 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
868 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
869
870 #define CLOCK_GPIO_OFFSET 0xffffffff
871 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
872 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
873
874 #define SI_CONFIG_OFFSET 0x00000000
875 #define SI_CONFIG_ERR_INT_LSB 19
876 #define SI_CONFIG_ERR_INT_MASK 0x00080000
877 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
878 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
879 #define SI_CONFIG_I2C_LSB 16
880 #define SI_CONFIG_I2C_MASK 0x00010000
881 #define SI_CONFIG_POS_SAMPLE_LSB 7
882 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
883 #define SI_CONFIG_INACTIVE_DATA_LSB 5
884 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
885 #define SI_CONFIG_INACTIVE_CLK_LSB 4
886 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
887 #define SI_CONFIG_DIVIDER_LSB 0
888 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
889 #define SI_CS_OFFSET 0x00000004
890 #define SI_CS_DONE_ERR_LSB 10
891 #define SI_CS_DONE_ERR_MASK 0x00000400
892 #define SI_CS_DONE_INT_LSB 9
893 #define SI_CS_DONE_INT_MASK 0x00000200
894 #define SI_CS_START_LSB 8
895 #define SI_CS_START_MASK 0x00000100
896 #define SI_CS_RX_CNT_LSB 4
897 #define SI_CS_RX_CNT_MASK 0x000000f0
898 #define SI_CS_TX_CNT_LSB 0
899 #define SI_CS_TX_CNT_MASK 0x0000000f
900
901 #define SI_TX_DATA0_OFFSET 0x00000008
902 #define SI_TX_DATA1_OFFSET 0x0000000c
903 #define SI_RX_DATA0_OFFSET 0x00000010
904 #define SI_RX_DATA1_OFFSET 0x00000014
905
906 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
907 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
908 #define CORE_CTRL_ADDRESS 0x0000
909 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
910 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
911 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address
912 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
913 #define CPU_INTR_ADDRESS 0x0010
914 #define FW_RAM_CONFIG_ADDRESS 0x0018
915
916 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
917
918 /* Firmware indications to the Host via SCRATCH_3 register. */
919 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address
920 #define FW_IND_EVENT_PENDING 1
921 #define FW_IND_INITIALIZED 2
922 #define FW_IND_HOST_READY 0x80000000
923
924 /* HOST_REG interrupt from firmware */
925 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask
926 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all
927
928 #define DRAM_BASE_ADDRESS 0x00400000
929
930 #define PCIE_BAR_REG_ADDRESS 0x40030
931
932 #define MISSING 0
933
934 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
935 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
936 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
937 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
938 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
939 #define RESET_CONTROL_MBOX_RST_MASK MISSING
940 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
941 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
942 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
943 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
944 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
945 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
946 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
947 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
948 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
949 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
950 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
951 #define LOCAL_SCRATCH_OFFSET 0x18
952 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
953 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
954 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
955 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
956 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
957 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
958 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
959 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
960 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
961 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
962 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
963 #define MBOX_BASE_ADDRESS MISSING
964 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
965 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
966 #define INT_STATUS_ENABLE_CPU_LSB MISSING
967 #define INT_STATUS_ENABLE_CPU_MASK MISSING
968 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
969 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
970 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
971 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
972 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
973 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
974 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
975 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
976 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
977 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
978 #define INT_STATUS_ENABLE_ADDRESS MISSING
979 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
980 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
981 #define HOST_INT_STATUS_ADDRESS MISSING
982 #define CPU_INT_STATUS_ADDRESS MISSING
983 #define ERROR_INT_STATUS_ADDRESS MISSING
984 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
985 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
986 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
987 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
988 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
989 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
990 #define COUNT_DEC_ADDRESS MISSING
991 #define HOST_INT_STATUS_CPU_MASK MISSING
992 #define HOST_INT_STATUS_CPU_LSB MISSING
993 #define HOST_INT_STATUS_ERROR_MASK MISSING
994 #define HOST_INT_STATUS_ERROR_LSB MISSING
995 #define HOST_INT_STATUS_COUNTER_MASK MISSING
996 #define HOST_INT_STATUS_COUNTER_LSB MISSING
997 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
998 #define WINDOW_DATA_ADDRESS MISSING
999 #define WINDOW_READ_ADDR_ADDRESS MISSING
1000 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
1001
1002 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5
1003 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3
1004 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17
1005 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3
1006 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
1007
1008 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0
1009 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00
1010 #define QCA9887_EEPROM_ADDR_HI_LSB 8
1011 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
1012 #define QCA9887_EEPROM_ADDR_LO_LSB 16
1013
1014 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000
1015 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800
1016 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7
1017 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080
1018 #define MBOX_HOST_INT_STATUS_CPU_LSB 6
1019 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040
1020 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4
1021 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010
1022 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801
1023 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802
1024 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2
1025 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
1026 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
1027 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
1028 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
1029 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
1030 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803
1031 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0
1032 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
1033 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805
1034 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828
1035 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7
1036 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
1037 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6
1038 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040
1039 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5
1040 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020
1041 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4
1042 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
1043 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
1044 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
1045 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819
1046 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0
1047 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1048 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a
1049 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
1050 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1051 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
1052 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
1053 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
1054 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
1055 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1056 #define MBOX_COUNT_ADDRESS 0x00000820
1057 #define MBOX_COUNT_DEC_ADDRESS 0x00000840
1058 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874
1059 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878
1060 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c
1061 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883
1062 #define MBOX_CPU_DBG_ADDRESS 0x00000884
1063 #define MBOX_RTC_BASE_ADDRESS 0x00000000
1064 #define MBOX_GPIO_BASE_ADDRESS 0x00005000
1065 #define MBOX_MBOX_BASE_ADDRESS 0x00008000
1066
1067 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1068
1069 /* Register definitions for first generation ath10k cards. These cards include
1070 * a mac thich has a register allocation similar to ath9k and at least some
1071 * registers including the ones relevant for modifying the coverage class are
1072 * identical to the ath9k definitions.
1073 * These registers are usually managed by the ath10k firmware. However by
1074 * overriding them it is possible to support coverage class modifications.
1075 */
1076 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014
1077 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF
1078 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF
1079 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0
1080 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000
1081 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16
1082
1083 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070
1084 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF
1085 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF
1086 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0
1087 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000
1088
1089 #define WAVE1_PHYCLK 0x801C
1090 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F
1091 #define WAVE1_PHYCLK_USEC_LSB 0
1092
1093 /* qca6174 PLL offset/mask */
1094 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114
1095 #define SOC_CORE_CLK_CTRL_DIV_LSB 0
1096 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007
1097
1098 #define EFUSE_OFFSET 0x0000032c
1099 #define EFUSE_XTAL_SEL_LSB 8
1100 #define EFUSE_XTAL_SEL_MASK 0x00000700
1101
1102 #define BB_PLL_CONFIG_OFFSET 0x000002f4
1103 #define BB_PLL_CONFIG_FRAC_LSB 0
1104 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff
1105 #define BB_PLL_CONFIG_OUTDIV_LSB 18
1106 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000
1107
1108 #define WLAN_PLL_SETTLE_OFFSET 0x0018
1109 #define WLAN_PLL_SETTLE_TIME_LSB 0
1110 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff
1111
1112 #define WLAN_PLL_CONTROL_OFFSET 0x0014
1113 #define WLAN_PLL_CONTROL_DIV_LSB 0
1114 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
1115 #define WLAN_PLL_CONTROL_REFDIV_LSB 10
1116 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00
1117 #define WLAN_PLL_CONTROL_BYPASS_LSB 16
1118 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
1119 #define WLAN_PLL_CONTROL_NOPWD_LSB 18
1120 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
1121
1122 #define RTC_SYNC_STATUS_OFFSET 0x0244
1123 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5
1124 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020
1125 /* qca6174 PLL offset/mask end */
1126
1127 #endif /* _HW_H_ */
1128
