| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 53 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
65 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
68 post_divider = 1; in rv730_populate_sclk_value()
70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
93 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
132 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
143 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
146 post_divider = 1; in rv730_populate_mclk_value()
168 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
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| D | rv6xx_dpm.c | 151 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
153 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
155 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
174 if (step->post_divider == 1) in rv6xx_output_stepping()
177 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
178 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()
200 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()
214 return (cur->post_divider > target->post_divider) && in rv6xx_can_step_post_div()
215 ((cur->vco_frequency * target->post_divider) <= in rv6xx_can_step_post_div()
216 (target->vco_frequency * (cur->post_divider - 1))); in rv6xx_can_step_post_div()
[all …]
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| D | rv6xx_dpm.h | 34 u32 post_divider; member
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| D | radeon_legacy_crtc.c | 739 uint32_t post_divider = 0; in radeon_set_pll() local
817 &reference_div, &post_divider); in radeon_set_pll()
820 if (post_div->divider == post_divider) in radeon_set_pll()
831 post_divider); in radeon_set_pll()
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| D | rv770_dpm.c | 325 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
333 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
337 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
502 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
514 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
516 post_divider = 1; in rv770_populate_sclk_value()
518 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
540 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
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| D | radeon_mode.h | 601 u32 post_divider; member
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| D | ci_dpm.c | 2671 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2679 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2712 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2745 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2777 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
3016 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3208 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
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| D | radeon_atombios.c | 2926 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in radeon_atom_get_clock_dividers()
2943 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()
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| D | cik.c | 9438 tmp |= dividers.post_divider; in cik_set_uvd_clock()
9485 tmp |= dividers.post_divider; in cik_set_vce_clocks()
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| /Linux-v4.19/drivers/video/fbdev/aty/ |
| D | mach64_gx.c | 346 u32 post_divider; in aty_var_to_pll_18818() local
352 post_divider = 1; in aty_var_to_pll_18818()
363 post_divider *= 2; in aty_var_to_pll_18818()
374 switch (post_divider) { in aty_var_to_pll_18818()
394 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()
560 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
679 pll->ics2595.post_divider = 0; in aty_var_to_pll_8398()
797 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_408()
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| D | radeon_monitor.c | 200 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
207 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
671 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
677 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
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| D | atyfb.h | 79 u32 post_divider; member
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| D | radeonfb.h | 265 int post_divider; member
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| D | aty128fb.c | 430 u32 post_divider; member
1354 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1392 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1408 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
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| D | radeon_base.c | 1709 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
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| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 129 uint32_t post_divider, in calculate_fb_and_fractional_fb_divider() argument
136 (uint64_t)target_pix_clk_khz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()
188 uint32_t post_divider, in calc_fb_divider_checking_tolerance() argument
201 post_divider, in calc_fb_divider_checking_tolerance()
212 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()
230 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()
234 actual_calculated_clock_khz * post_divider; in calc_fb_divider_checking_tolerance()
250 uint32_t post_divider; in calc_pll_dividers_in_range() local
261 post_divider = max_post_divider; in calc_pll_dividers_in_range()
262 post_divider >= min_post_divider; in calc_pll_dividers_in_range()
[all …]
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.h | 49 u32 post_divider; member
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| D | cik.c | 1314 tmp |= dividers.post_divider; in cik_set_uvd_clock()
1363 tmp |= dividers.post_divider; in cik_set_vce_clocks()
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| D | vi.c | 738 tmp |= dividers.post_divider; in vi_set_uvd_clock()
828 tmp |= dividers.post_divider; in vi_set_vce_clocks()
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| D | ci_dpm.c | 2809 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2817 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2850 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2883 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2915 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
3160 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3354 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
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| D | amdgpu_atombios.c | 1076 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1093 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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