| /Linux-v4.19/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1038 if (!pll->post_div_table) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1051 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1052 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1065 if (!pll->post_div_table) { in clk_alpha_pll_postdiv_fabia_round_rate()
1070 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1091 if (!pll->post_div_table) { in clk_alpha_pll_postdiv_fabia_set_rate()
1098 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1099 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
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| D | clk-alpha-pll.h | 82 const struct clk_div_table *post_div_table; member
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| D | gcc-sdm845.c | 204 .post_div_table = post_div_table_fabia_even,
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| /Linux-v4.19/drivers/clk/imx/ |
| D | clk-imx6sll.c | 59 static const struct clk_div_table post_div_table[] = { variable
168 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
172 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
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| D | clk-imx6sl.c | 82 static const struct clk_div_table post_div_table[] = { variable
266 …v", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
268 …v", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
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| D | clk-imx6q.c | 107 static struct clk_div_table post_div_table[] = { variable
430 post_div_table[1].div = 1; in imx6q_clocks_init()
431 post_div_table[2].div = 1; in imx6q_clocks_init()
541 …post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
543 …post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
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| D | clk-imx6ul.c | 90 static const struct clk_div_table post_div_table[] = { variable
219 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
223 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
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| D | clk-imx6sx.c | 103 static const struct clk_div_table post_div_table[] = { variable
252 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
256 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
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| D | clk-imx7d.c | 40 static const struct clk_div_table post_div_table[] = { variable
449 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
453 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
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